Lines Matching +full:0 +full:x98000000
24 reg = <0x80000000 0x40000000>;
34 reg = <0x98000000 0x04000000>; /* 64M */
40 gpios = <&gpio ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
101 #size-cells = <0>;
105 enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
106 clock-gpios = <&gpio ASPEED_GPIO(G, 0) GPIO_ACTIVE_HIGH>;
113 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
129 flash@0 {
141 pinctrl-0 = <&pinctrl_spi1_default>;
143 flash@0 {
154 pinctrl-0 = <&pinctrl_spi2ck_default
160 flash@0 {
168 pinctrl-0 = <&pinctrl_txd1_default
180 snoop-ports = <0x80>;
191 pinctrl-0 = <&pinctrl_rmii1_default>;
202 pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
210 reg = <0x50>;
216 reg = <0x68>;
221 reg = <0x64>;
236 reg = <0x71>;
238 #size-cells = <0>;
240 i2cpcie0: i2c@0 {
242 #size-cells = <0>;
243 reg = <0>;
247 #size-cells = <0>;
252 #size-cells = <0>;
257 #size-cells = <0>;
263 * PCIe 0
287 reg = <0x71>;
289 #size-cells = <0>;
291 i2cpcie3: i2c@0 {
293 #size-cells = <0>;
294 reg = <0>;
298 #size-cells = <0>;
333 reg = <0x70>;
337 #size-cells = <0>;
341 reg = <0x54>;
349 reg = <0x64>;
354 reg = <0x40>;
359 reg = <0x60>;
364 reg = <0x43>;
369 reg = <0x41>;
386 reg = <0x6a>;
390 reg = <0x30>;
408 reg = <0x64>;
413 reg = <0x40>;
418 reg = <0x41>;
423 reg = <0x42>;
428 reg = <0x60>;
479 pinctrl-0 = <&pinctrl_gpioh_unbiased>;
522 gpios = <ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
550 pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
553 fan@0 {
554 reg = <0x00>;
555 aspeed,fan-tach-ch = /bits/ 8 <0x00>;
559 reg = <0x01>;
560 aspeed,fan-tach-ch = /bits/ 8 <0x01>;
564 reg = <0x02>;
565 aspeed,fan-tach-ch = /bits/ 8 <0x02>;
569 reg = <0x03>;
570 aspeed,fan-tach-ch = /bits/ 8 <0x03>;