Lines Matching +full:0 +full:x98000000
16 reg = <0x80000000 0x20000000>;
26 reg = <0x9f000000 0x01000000>; /* 16M */
31 reg = <0x98000000 0x04000000>; /* 64M */
35 reg = <0x9ef00000 0x00100000>;
40 size = <0x01000000>;
41 alignment = <0x01000000>;
47 size = <0x02000000>; /* 32M */
48 alignment = <0x01000000>;
73 #size-cells = <0>;
80 clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
83 enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
111 flash@0 {
123 pinctrl-0 = <&pinctrl_spi1_default>;
125 flash@0 {
144 pinctrl-0 = <&pinctrl_txd1_default
164 pinctrl-0 = <&pinctrl_rmii1_default>;
220 reg = <0x32>;
229 reg = <0x4c>;
299 pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
301 fan@0 {
302 reg = <0x00>;
303 aspeed,fan-tach-ch = /bits/ 8 <0x08>;
307 reg = <0x00>;
308 aspeed,fan-tach-ch = /bits/ 8 <0x09>;
312 reg = <0x01>;
313 aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
317 reg = <0x01>;
318 aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
322 reg = <0x00>;
323 aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
327 reg = <0x00>;
328 aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
332 reg = <0x01>;
333 aspeed,fan-tach-ch = /bits/ 8 <0x0e>;