Lines Matching +full:0 +full:x10017000
44 /* 128 MiB memory @ 0x0 */
45 reg = <0x00000000 0x08000000>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
86 #clock-cells = <0>;
94 #clock-cells = <0>;
102 #clock-cells = <0>;
110 #clock-cells = <0>;
118 #clock-cells = <0>;
126 pclk: pclk@0 {
127 #clock-cells = <0>;
129 clock-frequency = <0>;
135 reg = <0x40000000 0x04000000>;
145 reg = <0x44000000 0x04000000>;
155 reg = <0x4e000000 0x10000>;
166 reg = <0x4f000000 0x20000>;
173 #size-cells = <0>;
177 #size-cells = <0>;
179 port@0 {
180 reg = <0>;
222 reg = <0x10000000 0x1000>;
223 ranges = <0x0 0x10000000 0x1000>;
227 led@8,0 {
229 reg = <0x08 0x04>;
230 offset = <0x08>;
231 mask = <0x01>;
232 label = "versatile:0";
238 reg = <0x08 0x04>;
239 offset = <0x08>;
240 mask = <0x02>;
247 reg = <0x08 0x04>;
248 offset = <0x08>;
249 mask = <0x04>;
256 reg = <0x08 0x04>;
257 offset = <0x08>;
258 mask = <0x08>;
264 reg = <0x08 0x04>;
265 offset = <0x08>;
266 mask = <0x10>;
272 reg = <0x08 0x04>;
273 offset = <0x08>;
274 mask = <0x20>;
280 reg = <0x08 0x04>;
281 offset = <0x08>;
282 mask = <0x40>;
288 reg = <0x08 0x04>;
289 offset = <0x08>;
290 mask = <0x80>;
296 reg = <0x0c 0x04>;
297 #clock-cells = <0>;
298 lock-offset = <0x20>;
299 vco-offset = <0x0C>;
304 reg = <0x10 0x04>;
305 #clock-cells = <0>;
306 lock-offset = <0x20>;
307 vco-offset = <0x10>;
312 reg = <0x14 0x04>;
313 #clock-cells = <0>;
314 lock-offset = <0x20>;
315 vco-offset = <0x14>;
320 reg = <0x18 0x04>;
321 #clock-cells = <0>;
322 lock-offset = <0x20>;
323 vco-offset = <0x18>;
328 reg = <0x1c 0x04>;
329 #clock-cells = <0>;
330 lock-offset = <0x20>;
331 vco-offset = <0x1c>;
338 reg = <0x10001000 0x1000>;
346 assigned-clocks = <&sp810_syscon0 0>,
358 #size-cells = <0>;
360 reg = <0x10002000 0x1000>;
364 reg = <0x68>;
370 reg = <0x10009000 0x1000>;
377 reg = <0x1000a000 0x1000>;
384 reg = <0x1000b000 0x1000>;
391 reg = <0x1000d000 0x1000>;
398 reg = <0x1000f000 0x1000>;
406 reg = <0x10010000 0x1000>;
414 reg = <0x10011000 0x1000>;
415 clocks = <&sp810_syscon0 0>,
425 reg = <0x10012000 0x1000>;
436 reg = <0x10013000 0x1000>;
447 reg = <0x10014000 0x1000>;
458 reg = <0x10015000 0x1000>;
469 #size-cells = <0>;
471 reg = <0x10016000 0x1000>;
476 reg = <0x10017000 0x1000>;
483 reg = <0x10018000 0x1000>;
490 reg = <0x10019000 0x1000>;
497 reg = <0x1001a000 0x1000>;
505 assigned-clocks = <&sp810_syscon1 0>,
526 reg = <0x10004000 0x1000>;
533 reg = <0x10005000 0x1000>;
543 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
549 reg = <0x10006000 0x1000>;
556 reg = <0x10007000 0x1000>;
563 reg = <0x1000c000 0x1000>;
578 reg = <0x10020000 0x1000>;
588 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;