Lines Matching +full:0 +full:x3c000000
45 /* 128 MiB memory @ 0x0 */
46 reg = <0x00000000 0x08000000>;
67 #clock-cells = <0>;
73 #clock-cells = <0>;
81 #clock-cells = <0>;
89 #clock-cells = <0>;
97 #clock-cells = <0>;
105 #clock-cells = <0>;
113 pclk: pclk@0 {
114 #clock-cells = <0>;
116 clock-frequency = <0>;
121 reg = <0x30000000 0x4000000>;
130 reg = <0x38000000 0x800000>;
145 reg = <0x3c000000 0x4000000>;
153 reg = <0x3a000000 0x10000>;
155 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
166 reg = <0x3b000000 0x20000>;
168 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
175 #size-cells = <0>;
179 #size-cells = <0>;
181 port@0 {
182 reg = <0>;
218 reg = <0x10000000 0x1000>;
219 ranges = <0x0 0x10000000 0x1000>;
223 led@8,0 {
225 reg = <0x08 0x04>;
226 offset = <0x08>;
227 mask = <0x01>;
228 label = "versatile:0";
234 reg = <0x08 0x04>;
235 offset = <0x08>;
236 mask = <0x02>;
243 reg = <0x08 0x04>;
244 offset = <0x08>;
245 mask = <0x04>;
252 reg = <0x08 0x04>;
253 offset = <0x08>;
254 mask = <0x08>;
260 reg = <0x08 0x04>;
261 offset = <0x08>;
262 mask = <0x10>;
268 reg = <0x08 0x04>;
269 offset = <0x08>;
270 mask = <0x20>;
276 reg = <0x08 0x04>;
277 offset = <0x08>;
278 mask = <0x40>;
284 reg = <0x08 0x04>;
285 offset = <0x08>;
286 mask = <0x80>;
292 reg = <0x0c 0x04>;
293 #clock-cells = <0>;
294 lock-offset = <0x20>;
295 vco-offset = <0x0C>;
300 reg = <0x10 0x04>;
301 #clock-cells = <0>;
302 lock-offset = <0x20>;
303 vco-offset = <0x10>;
308 reg = <0x14 0x04>;
309 #clock-cells = <0>;
310 lock-offset = <0x20>;
311 vco-offset = <0x14>;
316 reg = <0x18 0x04>;
317 #clock-cells = <0>;
318 lock-offset = <0x20>;
319 vco-offset = <0x18>;
324 reg = <0x1c 0x04>;
325 #clock-cells = <0>;
326 lock-offset = <0x20>;
327 vco-offset = <0x1c>;
338 reg = <0x10121000 0x1000>,
339 <0x10120000 0x100>;
344 reg = <0x10110000 0x1000>;
346 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
363 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
368 reg = <0x10104000 0x1000>;
370 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
377 reg = <0x10105000 0x1000>;
379 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
387 reg = <0x10108000 0x1000>;
389 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
396 reg = <0x1010a000 0x1000>;
399 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
409 reg = <0x1010b000 0x1000>;
411 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
418 reg = <0x1010c000 0x1000>;
420 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
427 reg = <0x1010d000 0x1000>;
429 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
436 reg = <0x1010e000 0x1000>;
438 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
445 reg = <0x1010f000 0x1000>;
447 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
455 reg = <0x10200000 0x4000>;
461 reg = <0x10112000 0x1000>;
464 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
473 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
488 #size-cells = <0>;
490 reg = <0x10002000 0x1000>;
494 reg = <0x68>;
500 reg = <0x10004000 0x1000>;
502 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
509 reg = <0x10005000 0x1000>;
511 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>,
512 <0 2 IRQ_TYPE_LEVEL_HIGH>;
521 cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>;
527 reg = <0x10006000 0x1000>;
529 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
536 reg = <0x10007000 0x1000>;
538 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
545 reg = <0x10008000 0x1000>;
547 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
554 reg = <0x10009000 0x1000>;
556 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
567 reg = <0x10041000 0x1000>,
568 <0x10040000 0x100>;
570 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
575 reg = <0x10014000 0x1000>;
578 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
588 reg = <0x10015000 0x1000>;
591 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
601 reg = <0x10017000 0x1000>;
603 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;