Lines Matching +full:0 +full:x1000b000
43 /* 128 MiB memory @ 0x0 */
44 reg = <0x00000000 0x08000000>;
48 vmmc: fixedregulator@0 {
57 #clock-cells = <0>;
63 #clock-cells = <0>;
71 #clock-cells = <0>;
79 #clock-cells = <0>;
87 #clock-cells = <0>;
95 #clock-cells = <0>;
103 #clock-cells = <0>;
111 pclk: pclk@0 {
112 #clock-cells = <0>;
114 clock-frequency = <0>;
120 reg = <0x40000000 0x04000000>;
130 reg = <0x44000000 0x04000000>;
140 reg = <0x4e000000 0x10000>;
150 reg = <0x4f000000 0x20000>;
157 #size-cells = <0>;
161 #size-cells = <0>;
163 port@0 {
164 reg = <0>;
200 reg = <0x10000000 0x1000>;
201 ranges = <0x0 0x10000000 0x1000>;
205 led@8,0 {
207 reg = <0x08 0x04>;
208 offset = <0x08>;
209 mask = <0x01>;
210 label = "versatile:0";
216 reg = <0x08 0x04>;
217 offset = <0x08>;
218 mask = <0x02>;
225 reg = <0x08 0x04>;
226 offset = <0x08>;
227 mask = <0x04>;
234 reg = <0x08 0x04>;
235 offset = <0x08>;
236 mask = <0x08>;
242 reg = <0x08 0x04>;
243 offset = <0x08>;
244 mask = <0x10>;
250 reg = <0x08 0x04>;
251 offset = <0x08>;
252 mask = <0x20>;
258 reg = <0x08 0x04>;
259 offset = <0x08>;
260 mask = <0x40>;
266 reg = <0x08 0x04>;
267 offset = <0x08>;
268 mask = <0x80>;
274 reg = <0x0c 0x04>;
275 #clock-cells = <0>;
276 lock-offset = <0x20>;
277 vco-offset = <0x0C>;
282 reg = <0x10 0x04>;
283 #clock-cells = <0>;
284 lock-offset = <0x20>;
285 vco-offset = <0x10>;
290 reg = <0x14 0x04>;
291 #clock-cells = <0>;
292 lock-offset = <0x20>;
293 vco-offset = <0x14>;
298 reg = <0x18 0x04>;
299 #clock-cells = <0>;
300 lock-offset = <0x20>;
301 vco-offset = <0x18>;
306 reg = <0x1c 0x04>;
307 #clock-cells = <0>;
308 lock-offset = <0x20>;
309 vco-offset = <0x1c>;
316 #size-cells = <0>;
318 reg = <0x10002000 0x1000>;
322 reg = <0x68>;
328 reg = <0x10004000 0x1000>;
335 reg = <0x10005000 0x1000>;
345 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
351 reg = <0x10006000 0x1000>;
358 reg = <0x10007000 0x1000>;
365 reg = <0x10008000 0x1000>;
372 reg = <0x10009000 0x1000>;
379 reg = <0x1000a000 0x1000>;
386 reg = <0x1000b000 0x1000>;
393 reg = <0x1000c000 0x1000>;
400 reg = <0x1000d000 0x1000>;
407 reg = <0x10010000 0x1000>;
415 reg = <0x10011000 0x1000>;
422 reg = <0x10012000 0x1000>;
429 reg = <0x10013000 0x1000>;
440 reg = <0x10014000 0x1000>;
451 reg = <0x10015000 0x1000>;
462 reg = <0x10017000 0x1000>;
469 reg = <0x10020000 0x1000>;
479 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;