Lines Matching +full:0 +full:x34000
20 memory@0 {
22 reg = <0 0>;
42 #size-cells = <0>;
43 cpu: cpu@0 {
47 reg = <0>;
76 opp-supported-hw = <0xFF 0x01>;
83 opp-supported-hw = <0xFF 0x04>;
89 opp-supported-hw = <0xFF 0x08>;
95 opp-supported-hw = <0xFF 0x10>;
101 opp-supported-hw = <0xFF 0x20>;
113 reg = <0x48241000 0x1000>,
114 <0x48240100 0x0100>;
122 reg = <0x48281000 0x1000>;
128 reg = <0x48240000 0x100>;
133 reg = <0x48240200 0x100>;
141 reg = <0x48240600 0x100>;
149 reg = <0x48242000 0x1000>;
157 clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>;
166 reg = <0x44000000 0x400000>,
167 <0x44800000 0x400000>;
181 reg = <0x4c000000 0x4>;
183 clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>;
188 ranges = <0x0 0x4c000000 0x1000000>;
190 emif: emif@0 {
192 reg = <0 0x1000000>;
201 reg = <0x49000000 0x4>;
203 clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
207 ranges = <0x0 0x49000000 0x10000>;
209 edma: dma@0 {
211 reg = <0 0x10000>;
222 <&edma_tptc2 0>;
230 reg = <0x49800000 0x4>,
231 <0x49800010 0x4>;
237 clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
241 ranges = <0x0 0x49800000 0x100000>;
243 edma_tptc0: dma@0 {
245 reg = <0 0x100000>;
253 reg = <0x49900000 0x4>,
254 <0x49900010 0x4>;
260 clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
264 ranges = <0x0 0x49900000 0x100000>;
266 edma_tptc1: dma@0 {
268 reg = <0 0x100000>;
276 reg = <0x49a00000 0x4>,
277 <0x49a00010 0x4>;
283 clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
287 ranges = <0x0 0x49a00000 0x100000>;
289 edma_tptc2: dma@0 {
291 reg = <0 0x100000>;
299 reg = <0x478102fc 0x4>,
300 <0x47810110 0x4>,
301 <0x47810114 0x4>;
311 clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
315 ranges = <0x0 0x47810000 0x1000>;
317 mmc3: mmc@0 {
321 reg = <0x0 0x1000>;
328 reg = <0x53100100 0x4>,
329 <0x53100110 0x4>,
330 <0x53100114 0x4>;
339 clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
343 ranges = <0x0 0x53100000 0x1000>;
345 sham: sham@0 {
347 reg = <0 0x300>;
348 dmas = <&edma 36 0>;
356 reg = <0x53501080 0x4>,
357 <0x53501084 0x4>,
358 <0x53501088 0x4>;
368 clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
372 ranges = <0x0 0x53501000 0x1000>;
374 aes: aes@0 {
376 reg = <0 0xa0>;
378 dmas = <&edma 6 0>,
379 <&edma 5 0>;
386 reg = <0x53701030 0x4>,
387 <0x53701034 0x4>,
388 <0x53701038 0x4>;
398 clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
402 ranges = <0 0x53701000 0x1000>;
404 des: des@0 {
406 reg = <0 0xa0>;
408 dmas = <&edma 34 0>,
409 <&edma 33 0>;
416 reg = <0x54426000 0x4>,
417 <0x54426004 0x4>;
427 clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
433 ranges = <0x0 0x54400000 0x80000>;
435 pruss1: pruss@0 {
437 reg = <0x0 0x40000>;
442 pruss1_mem: memories@0 {
443 reg = <0x0 0x2000>,
444 <0x2000 0x2000>,
445 <0x10000 0x8000>;
452 reg = <0x26000 0x2000>;
455 ranges = <0x0 0x26000 0x2000>;
459 #size-cells = <0>;
462 reg = <0x30>;
463 #clock-cells = <0>;
472 reg = <0x32000 0x58>;
477 reg = <0x20000 0x2000>;
491 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
496 reg = <0x34000 0x3000>,
497 <0x22000 0x400>,
498 <0x22400 0x100>;
505 reg = <0x38000 0x3000>,
506 <0x24000 0x400>,
507 <0x24400 0x100>;
514 reg = <0x32400 0x90>;
519 #size-cells = <0>;
525 reg = <0x40000 0x40000>;
531 reg = <0x40000 0x1000>,
532 <0x42000 0x1000>;
538 reg = <0x66000 0x2000>;
541 ranges = <0x0 0x66000 0x2000>;
545 #size-cells = <0>;
548 reg = <0x30>;
549 #clock-cells = <0>;
558 reg = <0x72000 0x58>;
564 reg = <0x60000 0x2000>;
578 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
583 reg = <0x74000 0x1000>,
584 <0x62000 0x400>,
585 <0x62400 0x100>;
592 reg = <0x78000 0x1000>,
593 <0x64000 0x400>,
594 <0x64400 0x100>;
603 reg = <0x50000000 4>,
604 <0x50000010 4>,
605 <0x50000014 4>;
611 clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>;
615 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
616 <0x00000000 0x00000000 0x40000000>; /* data */
620 dmas = <&edma 52 0>;
624 reg = <0x50000000 0x2000>;
640 reg = <0x47900000 0x4>,
641 <0x47900010 0x4>;
647 clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
651 ranges = <0x0 0x47900000 0x1000>,
652 <0x30000000 0x30000000 0x4000000>;
654 qspi: spi@0 {
656 reg = <0 0x100>,
657 <0x30000000 0x4000000>;
662 #size-cells = <0>;
663 interrupts = <0 138 0x4>;
670 clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>;
675 ranges = <0 0x40300000 0x40000>;
677 ocmcram: sram@0 {
679 reg = <0 0x40000>; /* 256k */
680 ranges = <0 0 0x40000>;
684 pm_sram_code: pm-code-sram@0 {
686 reg = <0x0 0x1000>;
692 reg = <0x1000 0x1000>;
700 reg = <0x5600fe00 0x4>,
701 <0x5600fe10 0x4>;
709 clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
712 resets = <&prm_gfx 0>;
716 ranges = <0 0x56000000 0x1000000>;
727 reg = <0x300 0x100>;
728 #power-domain-cells = <0>;
733 reg = <0x400 0x100>;
734 #power-domain-cells = <0>;
740 reg = <0x500 0x100>;
741 #power-domain-cells = <0>;
746 reg = <0x600 0x100>;
747 #power-domain-cells = <0>;
752 reg = <0x700 0x100>;
753 #power-domain-cells = <0>;
758 reg = <0x800 0x100>;
760 #power-domain-cells = <0>;
765 reg = <0x2000 0x100>;
767 #power-domain-cells = <0>;
772 reg = <0x4000 0x100>;
781 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>,
782 <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
784 timer@0 {
794 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>,
795 <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>;
797 timer@0 {