Lines Matching +full:mmp +full:- +full:timer
1 # SPDX-License-Identifier: GPL-2.0
144 The ARM series is a line of low-power-consumption RISC chip designs
146 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
147 manufactured, but legacy ARM-based PC hardware remains popular in
158 supported in LLD until version 14. The combined range is -/+ 256 MiB,
251 Patch phys-to-virt and virt-to-phys translation functions at
255 This can only be used with non-XIP MMU kernels where the base
302 bool "MMU-based Paged Memory Management Support"
305 Select if you want MMU-based virtualised addressing space
373 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
412 # This is sorted alphabetically by mach-* pathname. However, plat-*
414 # plat- suffix) or along side the corresponding mach-* source.
416 source "arch/arm/mach-actions/Kconfig"
418 source "arch/arm/mach-alpine/Kconfig"
420 source "arch/arm/mach-artpec/Kconfig"
422 source "arch/arm/mach-asm9260/Kconfig"
424 source "arch/arm/mach-aspeed/Kconfig"
426 source "arch/arm/mach-at91/Kconfig"
428 source "arch/arm/mach-axxia/Kconfig"
430 source "arch/arm/mach-bcm/Kconfig"
432 source "arch/arm/mach-berlin/Kconfig"
434 source "arch/arm/mach-clps711x/Kconfig"
436 source "arch/arm/mach-cns3xxx/Kconfig"
438 source "arch/arm/mach-davinci/Kconfig"
440 source "arch/arm/mach-digicolor/Kconfig"
442 source "arch/arm/mach-dove/Kconfig"
444 source "arch/arm/mach-ep93xx/Kconfig"
446 source "arch/arm/mach-exynos/Kconfig"
448 source "arch/arm/mach-footbridge/Kconfig"
450 source "arch/arm/mach-gemini/Kconfig"
452 source "arch/arm/mach-highbank/Kconfig"
454 source "arch/arm/mach-hisi/Kconfig"
456 source "arch/arm/mach-hpe/Kconfig"
458 source "arch/arm/mach-imx/Kconfig"
460 source "arch/arm/mach-iop32x/Kconfig"
462 source "arch/arm/mach-ixp4xx/Kconfig"
464 source "arch/arm/mach-keystone/Kconfig"
466 source "arch/arm/mach-lpc32xx/Kconfig"
468 source "arch/arm/mach-mediatek/Kconfig"
470 source "arch/arm/mach-meson/Kconfig"
472 source "arch/arm/mach-milbeaut/Kconfig"
474 source "arch/arm/mach-mmp/Kconfig"
476 source "arch/arm/mach-moxart/Kconfig"
478 source "arch/arm/mach-mstar/Kconfig"
480 source "arch/arm/mach-mv78xx0/Kconfig"
482 source "arch/arm/mach-mvebu/Kconfig"
484 source "arch/arm/mach-mxs/Kconfig"
486 source "arch/arm/mach-nomadik/Kconfig"
488 source "arch/arm/mach-npcm/Kconfig"
490 source "arch/arm/mach-nspire/Kconfig"
492 source "arch/arm/mach-omap1/Kconfig"
494 source "arch/arm/mach-omap2/Kconfig"
496 source "arch/arm/mach-orion5x/Kconfig"
498 source "arch/arm/mach-oxnas/Kconfig"
500 source "arch/arm/mach-pxa/Kconfig"
502 source "arch/arm/mach-qcom/Kconfig"
504 source "arch/arm/mach-rda/Kconfig"
506 source "arch/arm/mach-realtek/Kconfig"
508 source "arch/arm/mach-rpc/Kconfig"
510 source "arch/arm/mach-rockchip/Kconfig"
512 source "arch/arm/mach-s3c/Kconfig"
514 source "arch/arm/mach-s5pv210/Kconfig"
516 source "arch/arm/mach-sa1100/Kconfig"
518 source "arch/arm/mach-shmobile/Kconfig"
520 source "arch/arm/mach-socfpga/Kconfig"
522 source "arch/arm/mach-spear/Kconfig"
524 source "arch/arm/mach-sti/Kconfig"
526 source "arch/arm/mach-stm32/Kconfig"
528 source "arch/arm/mach-sunplus/Kconfig"
530 source "arch/arm/mach-sunxi/Kconfig"
532 source "arch/arm/mach-tegra/Kconfig"
534 source "arch/arm/mach-uniphier/Kconfig"
536 source "arch/arm/mach-ux500/Kconfig"
538 source "arch/arm/mach-versatile/Kconfig"
540 source "arch/arm/mach-vt8500/Kconfig"
542 source "arch/arm/mach-zynq/Kconfig"
544 # ARMv7-M architecture
553 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
562 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
563 with a range of available cores like Cortex-M3/M4/M7.
596 source "arch/arm/Kconfig-nommu"
614 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
617 Executing a SWP instruction to read-only memory does not set bit 11
635 This option enables the workaround for the 430973 Cortex-A8
638 same virtual address, whether due to self-modifying code or virtual
639 to physical address re-mapping, Cortex-A8 does not recover from the
640 stale interworking branch prediction. This results in Cortex-A8
645 available in non-secure mode.
652 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
659 register may not be available in non-secure mode.
666 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
670 workaround disables the write-allocate mode for the L2 cache via the
672 may not be available in non-secure mode.
679 This option enables the workaround for the 742230 Cortex-A9
683 the diagnostic register of the Cortex-A9 which causes the DMB
692 This option enables the workaround for the 742231 Cortex-A9
694 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
699 register of the Cortex-A9 which reduces the linefill issuing
707 This option enables the workaround for the 643719 Cortex-A9 (prior to
717 This option enables the workaround for the 720789 Cortex-A9 (prior to
730 This option enables the workaround for the 743622 Cortex-A9
732 optimisation in the Cortex-A9 Store Buffer may lead to data
734 register of the Cortex-A9 which disables the Store Buffer
744 This option enables the workaround for the 751472 Cortex-A9 (prior
754 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
757 can populate the micro-TLB with a stale entry which may be hit with
765 This option enables the workaround for the 754327 Cortex-A9 (prior to
773 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
778 hit-under-miss enabled). It sets the undocumented bit 31 in
780 register, thus disabling hit-under-miss without putting the
789 affecting Cortex-A9 MPCore with two or more processors (all
802 This option enables the workaround for the 764319 Cortex A-9 erratum.
813 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
820 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
823 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
833 This option enables the workaround for the 773022 Cortex-A15
843 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
845 - Cortex-A12 852422: Execution of a sequence of instructions might
847 any Cortex-A12 cores yet.
856 This option enables the workaround for the 821420 Cortex-A12
860 deadlock when the VMOV instructions are issued out-of-order.
866 This option enables the workaround for the 825619 Cortex-A12
869 and Device/Strongly-Ordered loads and stores might cause deadlock
875 This option enables the workaround for the 857271 Cortex-A12
883 This option enables the workaround for the 852421 Cortex-A17
893 - Cortex-A17 852423: Execution of a sequence of instructions might
895 any Cortex-A17 cores yet.
896 This is identical to Cortex-A12 erratum 852422. It is a separate
904 This option enables the workaround for the 857272 Cortex-A17 erratum.
906 This is identical to Cortex-A12 erratum 857271. It is a separate
944 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
954 This option should be selected by machines which have an SMP-
957 The only effect of this option is to make the SMP-related
961 bool "Symmetric Multi-Processing"
971 If you say N here, the kernel will run on uni- and multiprocessor
977 See also <file:Documentation/x86/i386/IO-APIC.rst>,
978 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
979 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
988 SMP kernels contain instructions which fail on non-SMP processors.
1015 bool "Multi-core scheduler support"
1018 Multi-core scheduler support improves the CPU scheduler's decision
1019 making when dealing with multi-core CPU chips at a cost of slightly
1036 bool "Architected timer support"
1040 This option enables support for the ARM architected timer
1045 This options enables support for the ARM timer and watchdog unit
1048 bool "Multi-Cluster Power Management"
1052 for (multi-)cluster based systems, such as big.LITTLE based
1128 int "Maximum number of CPUs (2-32)"
1136 debugging is enabled, which uses half of the per-CPU fixmap
1140 bool "Support for hot-pluggable CPUs"
1153 implementing the PSCI specification for CPU-centric power
1186 prompt "Timer frequency"
1222 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1228 Thumb-2 mode.
1318 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1326 user-space 2nd level page tables to reside in high memory.
1329 bool "Enable use of CPU domains to implement privileged no-access"
1335 use-after-free bugs becoming an exploitable privilege escalation
1339 CPUs with low-vector mappings use a best-efforts implementation.
1362 Disabling this is usually safe for small single-platform
1387 address divisible by 4. On 32-bit ARM processors, these non-aligned
1390 correct operation of some network protocols. With an IP-only
1399 cores where a 8-word STM instruction give significantly higher
1406 However, if the CPU data cache is using a write-allocate mode,
1446 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1495 https://lore.kernel.org/all/CAK8P3a0Z9vGEQbVRBo84bSyPFM-LF+hs5w8ZA51g2Z+NsdtDQA@mail.gmail.com/
1510 The physical address at which the ROM-able zImage is to be
1512 ROM-able zImage formats normally set this to a suitable
1522 for the ROM-able zImage which must be available while the
1525 Platforms which normally make use of ROM-able zImage formats
1577 Uses the command-line options passed by the boot loader instead of
1584 The command-line arguments provided by the boot loader will be
1595 architectures, you should supply some command-line options at build
1606 Uses the command-line options passed by the boot loader. If
1613 The command-line arguments provided by the boot loader will be
1622 command-line options your boot loader passes to the kernel.
1626 bool "Kernel Execute-In-Place from ROM"
1630 Execute-In-Place allows the kernel to run from non-volatile storage
1633 to RAM. Read-write sections, such as the data section and stack,
1695 loaded in the main kernel with kexec-tools into a specially
1700 For more details see Documentation/admin-guide/kdump/kdump.rst
1708 will be determined at run-time, either by masking the current IP
1726 by UEFI firmware (such as non-volatile variables, realtime
1741 continue to boot on existing non-UEFI platforms.
1747 to be enabled much earlier than we do on ARM, which is non-trivial.
1770 your machine has an FPA or floating point co-processor podule.
1779 Say Y to include 80-bit support in the kernel floating-point
1780 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1781 Note that gcc does not generate 80-bit operations by default,
1794 It is very simple, and approximately 3-6 times faster than NWFPE.
1802 bool "VFP-format floating point maths"
1808 Please see <file:Documentation/arm/vfp/release-notes.rst> for