Lines Matching +full:0022 +full:a
144 The ARM series is a line of low-power-consumption RISC chip designs
148 Europe. There is an ARM Linux project with a web page at
157 relocations, which have been around for a long time, but were not
175 size. This works well for buffers up to a few hundreds kilobytes, but
176 for larger buffers it just a waste of address space. Drivers which has
178 virtual space with just a few allocations.
182 specified order. The order is expressed as a power of two multiplied
256 of physical memory is at a 2 MiB boundary.
259 this feature (eg, building a kernel for a single machine) and
327 In general, all Arm machines can be supported in a single
373 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
563 with a range of available cores like Cortex-M3/M4/M7.
593 running on a CPU that supports it.
604 When coming out of either a Wait for Interrupt (WFI) or a Wait for
605 Event (WFE) IDLE states, a specific timing sensitivity exists between
607 instructions. This sensitivity can result in a CPU hang scenario.
609 The software must insert either a Data Synchronization Barrier (DSB)
614 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
617 Executing a SWP instruction to read-only memory does not set bit 11
619 treat the access as a read, preventing a COW from occurring and
636 r1p* erratum. If a code sequence containing an ARM/Thumb
648 bool "ARM errata: Processor deadlock when a false hazard is created"
654 possible for a hazard condition intended for a cache line to instead
655 be incorrectly associated with a different cache line. This false
656 hazard might then cause a processor deadlock. The workaround enables
667 erratum. Any asynchronous access to the L2 cache may encounter a
680 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
682 ordering of the two writes. This workaround sets a specific bit in
684 instruction to behave as a DSB, ensuring the correct behaviour of
714 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
718 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
720 As a consequence of this erratum, some TLB entries which should be
731 (r2p*) erratum. Under very rare conditions, a faulty
733 corruption. This workaround sets a specific bit in the diagnostic
746 completion of a following broadcasted operation if the second
747 operation is received by a CPU before the ICIALLUIS has completed,
755 r3p*) erratum. A speculative memory access may cause a page table walk
757 can populate the micro-TLB with a stale entry which may be hit with
767 mechanism and therefore a livelock may occur if an external agent
768 continuously polls a memory location waiting to observe an update.
790 current revisions). Under certain timing circumstances, a data
794 system. This workaround adds a DSB instruction before the
795 relevant cache maintenance functions and sets a specific bit
802 This option enables the workaround for the 764319 Cortex A-9 erratum.
806 from a privileged mode. This work around catches the exception in a
810 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
814 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
845 - Cortex-A12 852422: Execution of a sequence of instructions might
846 lead to either a data corruption or a CPU deadlock. Not fixed in
849 Feature Register. This bit disables an optimisation applied to a
853 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
857 (all revs) erratum. In very rare timing conditions, a sequence
859 one is in the shadow of a branch or abort, can lead to a
867 (all revs) erratum. Within rare timing constraints, executing a
868 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
877 hang. The workaround is expected to have a < 1% performance impact.
885 execution of a DMB ST instruction might fail to properly order
893 - Cortex-A17 852423: Execution of a sequence of instructions might
894 lead to either a data corruption or a CPU deadlock. Not fixed in
896 This is identical to Cortex-A12 erratum 852422. It is a separate
906 This is identical to Cortex-A12 erratum 857271. It is a separate
920 name of a bus system, i.e. the way the CPU talks to the other stuff
968 a system with only one CPU, say N. If you have a system with more
972 machines, but will use only one CPU of a multiprocessor machine. If
974 uniprocessor machines. On a uniprocessor machine, the kernel
1019 making when dealing with multi-core CPU chips at a cost of slightly
1027 MultiThreading at a cost of slightly increased overhead in some
1078 transparently handle transition between a cluster of A15's
1079 and a cluster of A7's in a big.LITTLE system.
1085 This is a simple and dummy char dev interface to control
1155 0022A ("Power State Coordination Interface System Software on
1159 # a multiplatform kernel, we just want the highest value required by the
1256 ARM ABI (aka EABI). This is only useful if you are using a user
1272 new (ARM EABI) one. It also provides a compatibility layer to
1275 (only for non "thumb" binaries). This option adds a tiny
1276 overhead to all syscalls and produces a slightly larger kernel.
1284 to execute a legacy ABI binary then the result will be
1307 have a large amount of physical memory and/or IO, not all of the
1313 option which should result in a slightly faster kernel.
1323 For systems with a lot of processes, this can use a lot of
1339 CPUs with low-vector mappings use a best-efforts implementation.
1372 blocks into "zones", where each zone is a power of two number of
1379 a value of 11 means that the largest free memory block is 2^10 pages.
1386 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1389 here, which has a severe performance impact. This is necessary for
1399 cores where a 8-word STM instruction give significantly higher
1400 memory write throughput than a sequence of individual 32bit stores.
1402 A possible side effect is a slight increase in scheduling latency
1406 However, if the CPU data cache is using a write-allocate mode,
1413 under a hypervisor, potentially improving performance significantly
1423 that, there can be a small performance impact.
1443 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1449 bool "Use a unique stack canary value for each task"
1461 Enable this option to switch to a different method that uses a
1490 by default now. If you are using a board file that is marked
1494 send a reply to the email discussion at
1512 ROM-able zImage formats normally set this to a suitable
1526 normally set this to a suitable value in their defconfig file.
1542 With this option, the boot code will look for a device tree binary
1546 This is meant as a backward compatibility convenience for those
1547 systems with a bootloader that can't be upgraded to accommodate
1548 the documented boot protocol using a device tree.
1552 look like a DTB header after a reboot if no actual DTB is appended
1553 to zImage. Do not leave this option active in a production kernel
1554 if you don't intend to always append a DTB. Proper passing of the
1555 location into r2 of a bootloader provided DTB is always preferable
1562 Some old bootloaders can't be updated to a DTB capable one, yet
1565 provided by the bootloader and can't always be stored in a static
1566 DTB. To allow a device tree enabled kernel to be used with such
1596 time by entering them here. As a minimum, you should specify the
1664 copied, saving some precious ROM space. A possible drawback is a
1673 kexec is a system call that implements the ability to shutdown your
1674 current kernel, and to start another kernel. It is like a reboot
1675 but it is independent of the system firmware. And like a reboot
1678 It is an ongoing process to be certain the hardware in a machine
1695 loaded in the main kernel with kexec-tools into a specially
1696 reserved region and then later executed after a crash by
1697 kdump/kexec. The crash dump kernel must be compiled to a
1727 clock, and platform reset). A UEFI stub is also provided to
1798 If you do not feel you need a faster FP emulation you should better
1806 if your hardware includes a VFP unit.