Lines Matching +full:axs10x +full:- +full:reset

1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
84 source "arch/arc/plat-tb10x/Kconfig"
85 source "arch/arc/plat-axs10x/Kconfig"
86 source "arch/arc/plat-hsdk/Kconfig"
104 	  ISA for the Next Generation ARC-HS cores
122 	  -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
124 	  -Caches: New Prog Model, Region Flush
125 	  -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
128 	bool "ARC-HS"
133 	    - SMP configurations of up to 4 cores with coherency
134 	    - Optional L2 Cache and IO-Coherency
135 	    - Revised Interrupt Architecture (multiple priorites, reg banks,
137 	    - MMUv4 (PIPT dcache, Huge Pages)
138 	    - Instructions for
149 	string "Override default -mcpu compiler flag"
152 	  Override default -mcpu=xxx compiler flag (which is set depending on
163 	bool "Symmetric Multi-Processing"
171 	int "Maximum number of CPUs (2-4096)"
176 	bool "Enable Halt-on-reset boot mode"
178 	  In SMP configuration cores can be configured as Halt-on-reset
179 	  or they could all start at same time. For Halt-on-reset, non
191 	  This IP block enables SMP in ARC-HS38 cores.
192 	  It provides for cross-core interrupts, multi-core debug
207 	  This option specifies "N", with Line-len = 2 power N
224 	  This can be used to over-ride the global I/D Cache Enable on a
225 	  per-page basis (but only for pages accessed via MMU such as
227 	  TLB entries have a per-page Cache Enable Bit.
272 	  Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
320 	# if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
340 	bool "Insn: SWAPE (endian-swap)"
357 	  Enable gcc to generate 64-bit load/store instructions
370 	  Depending on the configuration, CPU can contain accumulator reg-pair
399 	  DSP extension presence in HW, no support for DSP-enabled userspace
410 	  run DSP-enabled userspace applications
419 	  and AGU registers to run DSP-enabled userspace applications
445 	  -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
446 	  -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
472 	bool "Support for the 40-bit Physical Address Extension"
489 	  kernel-user gutter)
506 	  Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
518 	  Metaware Debugger. This can come in handy for Linux-host communication
545 	  Enable paranoid checks and self-test of both ARC-specific and generic