Lines Matching +full:1 +full:- +full:16

1 // SPDX-License-Identifier: GPL-2.0
44 mask >>= 16; in noritake_update_irq_hw()
53 noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16)); in noritake_enable_irq()
59 noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16))); in noritake_disable_irq()
77 | ((unsigned long) inw(0x54a) << 16) in noritake_device_interrupt()
87 pld &= pld - 1; /* clear least bit set */ in noritake_device_interrupt()
88 if (i < 16) { in noritake_device_interrupt()
101 irq = (vector - 0x800) >> 4; in noritake_srm_device_interrupt()
110 * So, here's this additional grotty hack... :-( in noritake_srm_device_interrupt()
112 if (irq >= 16) in noritake_srm_device_interrupt()
113 irq = irq + 1; in noritake_srm_device_interrupt()
129 for (i = 16; i < 48; ++i) { in noritake_init_irq()
143 * Summary @ 0x542, summary register #1:
146 * 1 QLOGIC ISP1020A SCSI
149 * 4 Interrupt Line A from slot 1
150 * 5 Interrupt line B from slot 1
165 * 1 OR of secondary bus ints
168 * 4 Interrupt Line C from slot 1
169 * 5 Interrupt line D from slot 1
184 * 7 Intel PCI-EISA bridge chip
185 * 8 DEC PCI-PCI bridge chip
187 * 12 PCI on board slot 1
191 * This two layered interrupt approach means that we allocate IRQ 16 and
201 /* note: IDSELs 16, 17, and 25 are CORELLE only */ in noritake_map_irq()
202 { 16+1, 16+1, 16+1, 16+1, 16+1}, /* IdSel 16, QLOGIC */ in noritake_map_irq()
203 { -1, -1, -1, -1, -1}, /* IdSel 17, S3 Trio64 */ in noritake_map_irq()
204 { -1, -1, -1, -1, -1}, /* IdSel 18, PCEB */ in noritake_map_irq()
205 { -1, -1, -1, -1, -1}, /* IdSel 19, PPB */ in noritake_map_irq()
206 { -1, -1, -1, -1, -1}, /* IdSel 20, ???? */ in noritake_map_irq()
207 { -1, -1, -1, -1, -1}, /* IdSel 21, ???? */ in noritake_map_irq()
208 { 16+2, 16+2, 16+3, 32+2, 32+3}, /* IdSel 22, slot 0 */ in noritake_map_irq()
209 { 16+4, 16+4, 16+5, 32+4, 32+5}, /* IdSel 23, slot 1 */ in noritake_map_irq()
210 { 16+6, 16+6, 16+7, 32+6, 32+7}, /* IdSel 24, slot 2 */ in noritake_map_irq()
211 { 16+8, 16+8, 16+9, 32+8, 32+9}, /* IdSel 25, slot 3 */ in noritake_map_irq()
212 /* The following 5 are actually on PCI bus 1, which is in noritake_map_irq()
213 across the built-in bridge of the NORITAKE only. */ in noritake_map_irq()
214 { 16+1, 16+1, 16+1, 16+1, 16+1}, /* IdSel 16, QLOGIC */ in noritake_map_irq()
215 { 16+8, 16+8, 16+9, 32+8, 32+9}, /* IdSel 17, slot 3 */ in noritake_map_irq()
216 {16+10, 16+10, 16+11, 32+10, 32+11}, /* IdSel 18, slot 4 */ in noritake_map_irq()
217 {16+12, 16+12, 16+13, 32+12, 32+13}, /* IdSel 19, slot 5 */ in noritake_map_irq()
218 {16+14, 16+14, 16+15, 32+14, 32+15}, /* IdSel 20, slot 6 */ in noritake_map_irq()
229 if (dev->bus->number == 0) { in noritake_swizzle()
230 slot = PCI_SLOT(dev->devfn); in noritake_swizzle()
232 /* Check for the built-in bridge */ in noritake_swizzle()
233 else if (PCI_SLOT(dev->bus->self->devfn) == 8) { in noritake_swizzle()
234 slot = PCI_SLOT(dev->devfn) + 15; /* WAG! */ in noritake_swizzle()
238 /* Must be a card-based bridge. */ in noritake_swizzle()
240 if (PCI_SLOT(dev->bus->self->devfn) == 8) { in noritake_swizzle()
241 slot = PCI_SLOT(dev->devfn) + 15; in noritake_swizzle()
247 dev = dev->bus->self; in noritake_swizzle()
249 slot = PCI_SLOT(dev->devfn); in noritake_swizzle()
250 } while (dev->bus->self); in noritake_swizzle()
276 code = mchk_header->code; in noritake_apecs_machine_check()
315 .vector_name = "Noritake-Primo",