Lines Matching +full:2 +full:- +full:layered
1 // SPDX-License-Identifier: GPL-2.0
48 mikasa_update_irq_hw(cached_irq_mask |= 1 << (d->irq - 16)); in mikasa_enable_irq()
54 mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (d->irq - 16))); in mikasa_disable_irq()
81 pld &= pld - 1; /* clear least bit set */ in mikasa_device_interrupt()
118 * 2 Interrupt Line C from slot 0
124 * 8 Interrupt Line A from slot 2
125 * 9 Interrupt Line B from slot 2
126 *10 Interrupt Line C from slot 2
127 *11 Interrupt Line D from slot 2
137 * 7 Intel PCI-EISA bridge chip
140 * 13 PCI on board slot 2
143 * This two layered interrupt approach means that we allocate IRQ 16 and
154 { -1, -1, -1, -1, -1}, /* IdSel 18, PCEB */ in mikasa_map_irq()
155 { -1, -1, -1, -1, -1}, /* IdSel 19, ???? */ in mikasa_map_irq()
156 { -1, -1, -1, -1, -1}, /* IdSel 20, ???? */ in mikasa_map_irq()
157 { -1, -1, -1, -1, -1}, /* IdSel 21, ???? */ in mikasa_map_irq()
158 { 16+0, 16+0, 16+1, 16+2, 16+3}, /* IdSel 22, slot 0 */ in mikasa_map_irq()
160 { 16+8, 16+8, 16+9, 16+10, 16+11}, /* IdSel 24, slot 2 */ in mikasa_map_irq()
187 code = mchk_header->code; in mikasa_apecs_machine_check()
226 .vector_name = "Mikasa-Primo",