Lines Matching +full:2 +full:- +full:layered
1 // SPDX-License-Identifier: GPL-2.0
37 static unsigned int cached_irq_mask = -1;
48 eb64p_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq)); in eb64p_enable_irq()
54 eb64p_update_irq_hw(d->irq, cached_irq_mask |= 1 << d->irq); in eb64p_disable_irq()
79 pld &= pld - 1; /* clear least bit set */ in eb64p_device_interrupt()
105 hwrpb->sys_variation |= 2L << 10; in eb64p_init_irq()
125 if (request_irq(16 + 5, no_action, 0, "isa-cascade", NULL)) in eb64p_init_irq()
126 pr_err("Failed to register isa-cascade interrupt\n"); in eb64p_init_irq()
138 * 2 Interrupt Line B from slot 0
149 * 2 Interrupt Line D from slot 1
162 * 8 Intel SIO PCI-ISA bridge chip
163 * 9 Tulip - DECchip 21040 Ethernet controller
166 * This two layered interrupt approach means that we allocate IRQ 16 and
177 {16+0, 16+0, 16+2, 16+4, 16+9}, /* IdSel 6, slot ?, ?? */ in eb64p_map_irq()
179 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ in eb64p_map_irq()