1 // SPDX-License-Identifier: GPL-2.0
43 	int ofs = (irq - 16) / 8;  in cabriolet_update_irq_hw()
44 	outb(mask >> (16 + ofs * 8), 0x804 + ofs);  in cabriolet_update_irq_hw()
50 	cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq));  in cabriolet_enable_irq()
56 	cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq);  in cabriolet_disable_irq()
73 	pld = inb(0x804) | (inb(0x805) << 8) | (inb(0x806) << 16);  in cabriolet_device_interrupt()
81 		pld &= pld - 1;	/* clear least bit set */  in cabriolet_device_interrupt()
85 			handle_irq(16 + i);  in cabriolet_device_interrupt()
106 		for (i = 16; i < 35; ++i) {  in common_init_irq()
114 	if (request_irq(16 + 4, no_action, 0, "isa-cascade", NULL))  in common_init_irq()
115 		pr_err("Failed to register isa-cascade interrupt\n");  in common_init_irq()
165  * the on-board NCR and Tulip chips.  In the code below, I have used
173  * In the table, -1 means don't assign an IRQ number.  This is usually
182 		{16+0, 16+0, 16+5,  16+9, 16+13},  /* IdSel 6,  slot 0, J25 */  in eb66p_map_irq()
183 		{16+1, 16+1, 16+6, 16+10, 16+14},  /* IdSel 7,  slot 1, J26 */  in eb66p_map_irq()
184 		{  -1,   -1,   -1,    -1,    -1},  /* IdSel 8,  SIO         */  in eb66p_map_irq()
185 		{16+2, 16+2, 16+7, 16+11, 16+15},  /* IdSel 9,  slot 2, J27 */  in eb66p_map_irq()
186 		{16+3, 16+3, 16+8, 16+12,  16+6}   /* IdSel 10, slot 3, J28 */  in eb66p_map_irq()
203  * In the table, -1 means don't assign an IRQ number.  This is usually
212 		{ 16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 5,  slot 2, J21 */  in cabriolet_map_irq()
213 		{ 16+0, 16+0, 16+5,  16+9, 16+13}, /* IdSel 6,  slot 0, J19 */  in cabriolet_map_irq()
214 		{ 16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7,  slot 1, J20 */  in cabriolet_map_irq()
215 		{   -1,   -1,   -1,    -1,    -1}, /* IdSel 8,  SIO         */  in cabriolet_map_irq()
216 		{ 16+3, 16+3, 16+8, 16+12, 16+16}  /* IdSel 9,  slot 3, J22 */  in cabriolet_map_irq()
225 	if (pc873xx_probe() == -1) {  in cabriolet_enable_ide()
255  * A bit is set by writing a "1" to the desired position in the mask
268  * ISA     +--------------------------------------------------------------+
269  * ADDRESS |   7   |   6   |   5   |   4   |   3   |   2  |   1   |   0   |
272  *         +--------------------------------------------------------------+
274  *         +--------------------------------------------------------------+
276  *         +--------------------------------------------------------------+
278  *         Note: The mask register is write-only.
283  *   7	 64 bit PCI option slot 1
296 		{ 16+2, 16+2, 16+9,  16+13, 16+17}, /* IdSel  5, slot 2, J20 */  in alphapc164_map_irq()
297 		{ 16+0, 16+0, 16+7,  16+11, 16+15}, /* IdSel  6, slot 0, J29 */  in alphapc164_map_irq()
298 		{ 16+1, 16+1, 16+8,  16+12, 16+16}, /* IdSel  7, slot 1, J26 */  in alphapc164_map_irq()
299 		{   -1,   -1,   -1,    -1,    -1},  /* IdSel  8, SIO */  in alphapc164_map_irq()
300 		{ 16+3, 16+3, 16+10, 16+14, 16+18}, /* IdSel  9, slot 3, J19 */  in alphapc164_map_irq()
301 		{ 16+6, 16+6, 16+6,  16+6,  16+6},  /* IdSel 10, USB */  in alphapc164_map_irq()
302 		{ 16+5, 16+5, 16+5,  16+5,  16+5}   /* IdSel 11, IDE */  in alphapc164_map_irq()