40  * floppy to DMA only via the scatter/gather window set up for 8MB
41  * ISA DMA, since the maximum ISA DMA address is 2GB-1.
44  * have less than 1GB of memory, floppy usage/performance will not
47 #define T2_DIRECTMAP_2G 1
62  * NOTE: Herein lie back-to-back mb instructions.  They are magic. 
107  *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
108  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
117  * Type 1:
119  *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
120  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
122  * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
157 			DBG(("mk_conf_addr: device (%d)>20, returning -1\n",  in mk_conf_addr()
159 			return -1;  in mk_conf_addr()
165 		/* Type 1 configuration cycle.  */  in mk_conf_addr()
166 		*type1 = 1;  in mk_conf_addr()
194 		mb();  in conf_read()
196 	mb();  in conf_read()
199 	mcheck_expected(cpu) = 1;  in conf_read()
201 	t2_mcheck_any_expected |= (1 << cpu);  in conf_read()
202 	mb();  in conf_read()
206 	mb();  in conf_read()
207 	mb();  /* magic */  in conf_read()
217 		t2_mcheck_last_taken |= (1 << cpu);  in conf_read()
219 		mb();  in conf_read()
223 	mb();  in conf_read()
228 		mb();  in conf_read()
246 		mb();  in conf_write()
248 	mb();  in conf_write()
251 	mcheck_expected(cpu) = 1;  in conf_write()
253 	t2_mcheck_any_expected |= (1 << cpu);  in conf_write()
254 	mb();  in conf_write()
258 	mb();  in conf_write()
259 	mb();  /* magic */  in conf_write()
269 		t2_mcheck_last_taken |= (1 << cpu);  in conf_write()
270 		mb();  in conf_write()
274 	mb();  in conf_write()
279 		mb();  in conf_write()
295 	mask = (size - 1) * 8;  in t2_read_config()
313 	mask = (size - 1) * 8;  in t2_write_config()
333 	temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20);  in t2_direct_map_window1()
335 	temp = (length - 1) & 0xfff00000UL;  in t2_direct_map_window1()
352 	/* Note we can only do 1 SG window, as the other is for direct, so  in t2_sg_map_window2()
357 	temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20);  in t2_sg_map_window2()
359 	temp = (length - 1) & 0xfff00000UL;  in t2_sg_map_window2()
361 	*(vulp)T2_TBASE2 = virt_to_phys(hose->sg_isa->ptes) >> 1;  in t2_sg_map_window2()
362 	mb();  in t2_sg_map_window2()
364 	t2_pci_tbi(hose, 0, -1); /* flush TLB all */  in t2_sg_map_window2()
394 	t2_saved_config.window[1].wbase = *(vulp)T2_WBASE2;  in t2_save_configuration()
395 	t2_saved_config.window[1].wmask = *(vulp)T2_WMASK2;  in t2_save_configuration()
396 	t2_saved_config.window[1].tbase = *(vulp)T2_TBASE2;  in t2_save_configuration()
426 		mb();	  in t2_init_arch()
454 	 * Window 1 is direct mapped.  in t2_init_arch()
466 	*(vulp)T2_HAE_1 = 0; mb(); /* Sparse MEM HAE */  in t2_init_arch()
467 	*(vulp)T2_HAE_2 = 0; mb(); /* Sparse I/O HAE */  in t2_init_arch()
468 	*(vulp)T2_HAE_3 = 0; mb(); /* Config Space HAE */  in t2_init_arch()
479 	*(vulp)T2_HAE_4 = 0; mb();  in t2_init_arch()
491 	*(vulp)T2_WBASE2 = t2_saved_config.window[1].wbase;  in t2_kill_arch()
492 	*(vulp)T2_WMASK2 = t2_saved_config.window[1].wmask;  in t2_kill_arch()
493 	*(vulp)T2_TBASE2 = t2_saved_config.window[1].tbase;  in t2_kill_arch()
494 	mb();  in t2_kill_arch()
501 	mb();  in t2_kill_arch()
514 	mb();  in t2_pci_tbi()
519 	mb();  in t2_pci_tbi()
523 #define SIC_SEIC (1UL << 33)    /* System Event Clear */
543 	mb();  in t2_clear_errors()
544 	mb();  /* magic */  in t2_clear_errors()
565 	mb();  in t2_machine_check()
566 	mb();  /* magic */  in t2_machine_check()
573 	mb();  in t2_machine_check()
584 		if (alpha_verbose_mcheck > 1) {  in t2_machine_check()
595 		if (t2_mcheck_last_taken & (1 << cpu)) {  in t2_machine_check()
597 		    if (alpha_verbose_mcheck > 1) {  in t2_machine_check()
605 		    mb();  in t2_machine_check()
609 			mb();  in t2_machine_check()
614 	if (alpha_verbose_mcheck > 1) {  in t2_machine_check()