34  * NOTE: Herein lie back-to-back mb instructions.  They are magic. 
57  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
69  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
118 	mb();  in conf_read()
125 		mb();  in conf_read()
129 	mb();  in conf_read()
133 	mb();  in conf_read()
137 	mb();  in conf_read()
138 	mb();  /* magic */  in conf_read()
142 		mb();  in conf_read()
145 	mb();  in conf_read()
150 		mb();  in conf_read()
172 	mb();  in conf_write()
179 		mb();  in conf_write()
183 	mb();  in conf_write()
187 	mb();  in conf_write()
191 	mb();  in conf_write()
195 	mb();  in conf_write()
200 		mb();  in conf_write()
261 	mb();  in cia_pci_tbi()
291 	mb();  in cia_pci_tbi_try2()
294 	mb();  in cia_pci_tbi_try2()
296 	mb();  in cia_pci_tbi_try2()
306 	   though the lock bits are cleared. Tags 4-7 are "quite LRU" though,  in cia_pci_tbi_try2()
307 	   so use them and read at window 3 base exactly 4 times. Reading  in cia_pci_tbi_try2()
310 	bus_addr = cia_ioremap(CIA_BROKEN_TBIA_BASE, 32768 * 4);  in cia_pci_tbi_try2()
320 	mb();  in cia_pci_tbi_try2()
322 	mb();  in cia_pci_tbi_try2()
324 	mb();  in cia_pci_tbi_try2()
352 	static int page[PAGE_SIZE/4]  in verify_tb_operation()
366 	mb();  in verify_tb_operation()
369 	mb();  in verify_tb_operation()
371 	mb();  in verify_tb_operation()
383 	*(vip)CIA_IOC_TB_TAGn(4) = 0;  in verify_tb_operation()
391 	mb();  in verify_tb_operation()
430 	mb();  in verify_tb_operation()
432 	mb();  in verify_tb_operation()
434 	mb();  in verify_tb_operation()
464 	arena->ptes[4] = pte0;  in verify_tb_operation()
467 	mb();  in verify_tb_operation()
468 	temp = cia_readl(bus_addr + 4*PAGE_SIZE);  in verify_tb_operation()
469 	mb();  in verify_tb_operation()
471 	mb();  in verify_tb_operation()
491 	mb();  in verify_tb_operation()
493 	mb();  in verify_tb_operation()
495 	mb();  in verify_tb_operation()
500 		   on 4 page boundaries.  */  in verify_tb_operation()
501 		arena->align_entry = 4;  in verify_tb_operation()
515 	mb();  in verify_tb_operation()
517 	mb();  in verify_tb_operation()
519 	mb();  in verify_tb_operation()
524 	arena->ptes[4] = 0;  in verify_tb_operation()
546 	mb();  in verify_tb_operation()
548 	mb();  in verify_tb_operation()
550 	mb();  in verify_tb_operation()
576     } window[4];
597 	for (i = 0; i < 4; i++) {  in cia_save_srm_settings()
602 	mb();  in cia_save_srm_settings()
610 	for (i = 0; i < 4; i++) {  in cia_restore_srm_settings()
625 	mb();  in cia_restore_srm_settings()
680 	mb();  in do_init_arch()
718 	 * Window 0 is S/G 8MB at 8MB (for isa)  in do_init_arch()
719 	 * Window 1 is S/G 1MB at 768MB (for tbia) (unused for CIA rev 1)  in do_init_arch()
721 	 * Window 3 is DAC access 4GB at 8GB (or S/G for tbia if CIA rev 1)  in do_init_arch()
725 	 * from the 8K alignment one would expect for an 8MB window.   in do_init_arch()
747 	   are compared against W_DAC.  We can, however, directly map 4GB,  in do_init_arch()
750 	   4GB covers all of physical memory.  in do_init_arch()
831 	mb();  in cia_pci_clr_err()
863 		lock = (cia->pci_err0 >> 4) & 1;  in cia_decode_pci_error()
957 	tmp |= ((cia->mem_err1 >> 20) & 1) << 4;  in cia_decode_mem_error()
1007 	case 0x04: set_select = "Set 4 selected"; break;  in cia_decode_mem_error()
1135 	case 4: /* CIA_ERR_PCI_SERR */  in cia_decode_mchk()
1205 	mb();  in cia_machine_check()
1206 	mb();  /* magic */  in cia_machine_check()
1210 	mb();  in cia_machine_check()