34  * NOTE: Herein lie back-to-back mb instructions.  They are magic. 
56  *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
57  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
64  * 	 7:2	Register number
68  *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
69  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
78  *	 7:2	register number
85  *	doesn't get shifted by 2 bits as we want to "drop" the bottom two
118 	mb();  in conf_read()
125 		mb();  in conf_read()
129 	mb();  in conf_read()
133 	mb();  in conf_read()
137 	mb();  in conf_read()
138 	mb();  /* magic */  in conf_read()
142 		mb();  in conf_read()
145 	mb();  in conf_read()
150 		mb();  in conf_read()
172 	mb();  in conf_write()
179 		mb();  in conf_write()
183 	mb();  in conf_write()
187 	mb();  in conf_write()
191 	mb();  in conf_write()
195 	mb();  in conf_write()
200 		mb();  in conf_write()
251  * CIA Pass 1 and PYXIS Pass 1 and 2 have a broken scatter-gather tlb.
261 	mb();  in cia_pci_tbi()
291 	mb();  in cia_pci_tbi_try2()
294 	mb();  in cia_pci_tbi_try2()
296 	mb();  in cia_pci_tbi_try2()
320 	mb();  in cia_pci_tbi_try2()
322 	mb();  in cia_pci_tbi_try2()
324 	mb();  in cia_pci_tbi_try2()
346 	*(vip)CIA_IOC_PCI_Tn_BASE(window) = virt_to_phys(ppte) >> 2;  in cia_prepare_tbia_workaround()
366 	mb();  in verify_tb_operation()
369 	mb();  in verify_tb_operation()
371 	mb();  in verify_tb_operation()
381 	*(vip)CIA_IOC_TB_TAGn(2) = 0;  in verify_tb_operation()
389 	*(vip)CIA_IOC_TBn_PAGEm(0,2) = 0;  in verify_tb_operation()
391 	mb();  in verify_tb_operation()
430 	mb();  in verify_tb_operation()
432 	mb();  in verify_tb_operation()
434 	mb();  in verify_tb_operation()
467 	mb();  in verify_tb_operation()
469 	mb();  in verify_tb_operation()
471 	mb();  in verify_tb_operation()
491 	mb();  in verify_tb_operation()
493 	mb();  in verify_tb_operation()
495 	mb();  in verify_tb_operation()
515 	mb();  in verify_tb_operation()
517 	mb();  in verify_tb_operation()
519 	mb();  in verify_tb_operation()
532 		*(vip)CIA_IOC_TB_TAGn(0) = 2;  in verify_tb_operation()
533 		*(vip)CIA_IOC_TB_TAGn(1) = 2;  in verify_tb_operation()
534 		*(vip)CIA_IOC_TB_TAGn(2) = 2;  in verify_tb_operation()
535 		*(vip)CIA_IOC_TB_TAGn(3) = 2;  in verify_tb_operation()
546 	mb();  in verify_tb_operation()
548 	mb();  in verify_tb_operation()
550 	mb();  in verify_tb_operation()
602 	mb();  in cia_save_srm_settings()
625 	mb();  in cia_restore_srm_settings()
680 	mb();  in do_init_arch()
718 	 * Window 0 is S/G 8MB at 8MB (for isa)  in do_init_arch()
719 	 * Window 1 is S/G 1MB at 768MB (for tbia) (unused for CIA rev 1)  in do_init_arch()
720 	 * Window 2 is direct access 2GB at 2GB  in do_init_arch()
725 	 * from the 8K alignment one would expect for an 8MB window.   in do_init_arch()
737 	*(vip)CIA_IOC_PCI_T0_BASE = virt_to_phys(hose->sg_isa->ptes) >> 2;  in do_init_arch()
741 	*(vip)CIA_IOC_PCI_T2_BASE = 0 >> 2;  in do_init_arch()
768 		*(vip)CIA_IOC_PCI_T3_BASE = 0 >> 2;  in do_init_arch()
831 	mb();  in cia_pci_clr_err()
854 			"Window 2 hit", "Window 3 hit", "Monster window hit"  in cia_decode_pci_error()
1005 	case 0x02: set_select = "Set 2 selected"; break;  in cia_decode_mem_error()
1129 	case 2: /* CIA_ERR_CPU_PE */  in cia_decode_mchk()
1205 	mb();  in cia_machine_check()
1206 	mb();  /* magic */  in cia_machine_check()
1210 	mb();  in cia_machine_check()