34  * NOTE: Herein lie back-to-back mb instructions.  They are magic. 
56  *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
57  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
66  * Type 1:
68  *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
69  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
71  * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
118 	mb();  in conf_read()
124 		*(vip)CIA_IOC_CFG = (cia_cfg & ~3) | 1;  in conf_read()
125 		mb();  in conf_read()
129 	mb();  in conf_read()
131 	mcheck_expected(0) = 1;  in conf_read()
133 	mb();  in conf_read()
137 	mb();  in conf_read()
138 	mb();  /* magic */  in conf_read()
142 		mb();  in conf_read()
145 	mb();  in conf_read()
150 		mb();  in conf_read()
172 	mb();  in conf_write()
178 		*(vip)CIA_IOC_CFG = (cia_cfg & ~3) | 1;  in conf_write()
179 		mb();  in conf_write()
183 	mb();  in conf_write()
185 	mcheck_expected(0) = 1;  in conf_write()
187 	mb();  in conf_write()
191 	mb();  in conf_write()
195 	mb();  in conf_write()
200 		mb();  in conf_write()
220 	mask = (size - 1) * 8;  in cia_read_config()
238 	mask = (size - 1) * 8;  in cia_write_config()
251  * CIA Pass 1 and PYXIS Pass 1 and 2 have a broken scatter-gather tlb.
261 	mb();  in cia_pci_tbi()
268  * SG DMA operation in progress. This is true at least for PYXIS rev. 1,
291 	mb();  in cia_pci_tbi_try2()
294 	mb();  in cia_pci_tbi_try2()
296 	mb();  in cia_pci_tbi_try2()
303 	/* Even better - as seen on the PYXIS rev 1 the TLB tags 0-3 can  in cia_pci_tbi_try2()
320 	mb();  in cia_pci_tbi_try2()
322 	mb();  in cia_pci_tbi_try2()
324 	mb();  in cia_pci_tbi_try2()
333 	/* Use minimal 1K map. */  in cia_prepare_tbia_workaround()
338 	pte = (virt_to_phys(ppte) >> (PAGE_SHIFT - 1)) | 1;  in cia_prepare_tbia_workaround()
345 	  = (CIA_BROKEN_TBIA_SIZE*1024 - 1) & 0xfff00000;  in cia_prepare_tbia_workaround()
363 		use_tbia_try2 = 1;  in verify_tb_operation()
366 	mb();  in verify_tb_operation()
369 	mb();  in verify_tb_operation()
371 	mb();  in verify_tb_operation()
376 	tag0 = addr0 | 1;  in verify_tb_operation()
377 	pte0 = (virt_to_phys(page) >> (PAGE_SHIFT - 1)) | 1;  in verify_tb_operation()
380 	*(vip)CIA_IOC_TB_TAGn(1) = 0;  in verify_tb_operation()
388 	*(vip)CIA_IOC_TBn_PAGEm(0,1) = 0;  in verify_tb_operation()
391 	mb();  in verify_tb_operation()
410 	temp = *(vip)CIA_IOC_TB_TAGn(1);  in verify_tb_operation()
428 	mcheck_expected(0) = 1;  in verify_tb_operation()
430 	mb();  in verify_tb_operation()
432 	mb();  in verify_tb_operation()
434 	mb();  in verify_tb_operation()
449 		cia_pci_tbi(arena->hose, 0, -1);  in verify_tb_operation()
451 		if (temp & 1) {  in verify_tb_operation()
452 			use_tbia_try2 = 1;  in verify_tb_operation()
465 	mcheck_expected(0) = 1;  in verify_tb_operation()
467 	mb();  in verify_tb_operation()
469 	mb();  in verify_tb_operation()
471 	mb();  in verify_tb_operation()
489 	mcheck_expected(0) = 1;  in verify_tb_operation()
491 	mb();  in verify_tb_operation()
493 	mb();  in verify_tb_operation()
495 	mb();  in verify_tb_operation()
513 	mcheck_expected(0) = 1;  in verify_tb_operation()
515 	mb();  in verify_tb_operation()
517 	mb();  in verify_tb_operation()
519 	mb();  in verify_tb_operation()
533 		*(vip)CIA_IOC_TB_TAGn(1) = 2;  in verify_tb_operation()
539 	alpha_mv.mv_pci_tbi(arena->hose, 0, -1);  in verify_tb_operation()
546 	mb();  in verify_tb_operation()
548 	mb();  in verify_tb_operation()
550 	mb();  in verify_tb_operation()
602 	mb();  in cia_save_srm_settings()
625 	mb();  in cia_restore_srm_settings()
680 	mb();  in do_init_arch()
718 	 * Window 0 is S/G 8MB at 8MB (for isa)  in do_init_arch()
719 	 * Window 1 is S/G 1MB at 768MB (for tbia) (unused for CIA rev 1)  in do_init_arch()
721 	 * Window 3 is DAC access 4GB at 8GB (or S/G for tbia if CIA rev 1)  in do_init_arch()
725 	 * from the 8K alignment one would expect for an 8MB window.   in do_init_arch()
736 	*(vip)CIA_IOC_PCI_W0_MASK = (hose->sg_isa->size - 1) & 0xfff00000;  in do_init_arch()
739 	*(vip)CIA_IOC_PCI_W2_BASE = __direct_map_base | 1;  in do_init_arch()
740 	*(vip)CIA_IOC_PCI_W2_MASK = (__direct_map_size - 1) & 0xfff00000;  in do_init_arch()
752 	   On CIA rev 1, apparently W1 and W2 can't be used for SG.   in do_init_arch()
757 	tbia_window = 1;  in do_init_arch()
760 	} else if (cia_rev == 1) {  in do_init_arch()
766 		*(vip)CIA_IOC_PCI_W3_BASE = 0x00000000 | 1 | 8;  in do_init_arch()
806 	do_init_arch(1);  in pyxis_init_arch()
831 	mb();  in cia_pci_clr_err()
853 			"No window active", "Window 0 hit", "Window 1 hit",  in cia_decode_pci_error()
863 		lock = (cia->pci_err0 >> 4) & 1;  in cia_decode_pci_error()
864 		dac = (cia->pci_err0 >> 5) & 1;  in cia_decode_pci_error()
912 		dac = (cia->pci_err0 >> 28) & 1;  in cia_decode_pci_error()
946 	if ((cia->mem_err1 >> 20) & 1)  in cia_decode_mem_error()
957 	tmp |= ((cia->mem_err1 >> 20) & 1) << 4;  in cia_decode_mem_error()
1004 	case 0x01: set_select = "Set 1 selected"; break;  in cia_decode_mem_error()
1043 		i = ffs(syn) - 1;  in cia_decode_ecc_error()
1097 	par = (cia->cpu_err1 >> 21) & 1;  in cia_decode_parity_error()
1120 		return 1;  in cia_decode_mchk()
1122 	switch (ffs(cia->cia_err & 0xfff) - 1) {  in cia_decode_mchk()
1126 	case 1: /* CIA_ERR_UN_COR_ERR */  in cia_decode_mchk()
1196 	return 1;  in cia_decode_mchk()
1205 	mb();  in cia_machine_check()
1206 	mb();  /* magic */  in cia_machine_check()
1210 	mb();  in cia_machine_check()