31  * NOTE: Herein lie back-to-back mb instructions.  They are magic. 
59  *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
60  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
67  * 	 7:2	Register number
71  *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 
72  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
81  *	 7:2	register number
88  *	doesn't get shifted by 2 bits as we want to "drop" the bottom two
140 	mb();  in conf_read()
143 	/* If Type1 access, must set HAE #2. */  in conf_read()
146 		mb();  in conf_read()
154 	mb();  in conf_read()
159 	asm volatile("ldl %0,%1; mb; mb" : "=r"(value) : "m"(*(vuip)addr)  in conf_read()
165 		mb();  in conf_read()
168 	mb();  in conf_read()
192 		mb();  in conf_read()
198 	/* If Type1 access, must reset HAE #2 so normal IO space ops work.  */  in conf_read()
201 		mb();  in conf_read()
220 	mb();  in conf_write()
222 	/* If Type1 access, must set HAE #2. */  in conf_write()
225 		mb();  in conf_write()
231 	mb();  in conf_write()
235 	mb();  in conf_write()
236 	mb();  /* magic */  in conf_write()
238 	mb();  in conf_write()
261 		mb();  in conf_write()
266 	/* If Type1 access, must reset HAE #2 so normal IO space ops work.  */  in conf_write()
269 		mb();  in conf_write()
321 	mb();  in apecs_pci_tbi()
347 	 * Window 2 is scatter-gather 8MB at 8MB (for isa)  in apecs_init_arch()
372 	mb();  in apecs_init_arch()
384 		mb();  in apecs_pci_clr_err()
388 	mb();  in apecs_pci_clr_err()
410 	mb();  in apecs_machine_check()
411 	mb(); /* magic */  in apecs_machine_check()
415 	mb();  in apecs_machine_check()