Lines Matching +full:high +full:- +full:level

1 .. SPDX-License-Identifier: GPL-2.0
4 5-level paging
9 Original x86-64 was limited by 4-level paging to 256 TiB of virtual address
14 5-level paging. It is a straight-forward extension of the current page
20 QEMU 2.9 and later support 5-level paging.
22 Virtual memory layout for 5-level paging is described in
26 Enabling 5-level paging
30 Kernel with CONFIG_X86_5LEVEL=y still able to boot on 4-level hardware.
31 In this case additional page table level -- p4d -- will be folded at
34 User-space and large virtual address space
36 On x86, 5-level paging enables 56-bit userspace virtual address space.
39 information. It collides with valid pointers with 5-level paging and
43 above 47-bit by default.
46 specifying hint address (with or without MAP_FIXED) above 47-bits.
48 If hint address set above 47-bit, but MAP_FIXED is not specified, we try
51 from 47-bit window.
53 A high hint address would only affect the allocation in question, but not
56 Specifying high hint address on older kernel or on machine without 5-level
58 to allocation from 47-bit address space.
65 MPX (without MAWA extension) cannot handle addresses above 47-bit, so we