Lines Matching full:hardware

31 Shared Hardware Workqueues
36 Machines (VM's). This allows better hardware utilization vs. hard
38 allow the hardware to distinguish the context for which work is being
39 executed in the hardware by SWQ interface, SIOV uses Process Address Space
56 command was accepted by hardware. This allows the submitter to know if the
61 to the hardware and also permits hardware to be aware of application context
68 user processes and the rest of the hardware. When an application first
94 platform hardware.  ENQCMD uses the PASID stored in this MSR to tag requests
153  * Devices have a limited number (~10's to 1000's) of hardware workqueues.
154    The device driver manages allocating hardware workqueues.
155  * A single mmap() maps a single hardware workqueue as a "portal" and
162    which case they still share one device hardware workqueue.
172 Shared Virtual Addressing (SVA) permits I/O hardware and the processor to
186 Traditionally, in order for userspace applications to interact with hardware,
187 there is a separate hardware instance required per process. For example,
188 consider doorbells as a mechanism of informing hardware about work to process.
190 isolation. This requires hardware to provision that space and reserve it in
192 hardware also manages the queue depth for Shared Work Queues (SWQ), and
203 SWQ allows hardware to provision just a single address in the device. When
212 initialization of the hardware. User space only needs to worry about
218 hardware interfaces for virtualizing hardware. Hence, it's required to be
228 hardware to optimize device resource creation and can grow dynamically on
235 duplicated hardware for PCI config space and interrupts such as MSI-X.
253 When devices support SVA along with platform hardware such as IOMMU
260 but there is no page allocated by the OS, IOMMU hardware returns that no