Lines Matching +full:right +full:- +full:aligned

1 .. SPDX-License-Identifier: GPL-2.0
4 KVM-specific MSRs
16 ---------------
24 	4-byte alignment physical address of a memory area which must be
42 		An odd version indicates an in-progress update.
53 	Note that although MSRs are per-CPU entities, the effect of this
63 	4-byte aligned physical address of a memory area which must be in
80 	updates of this structure is arbitrary and implementation-dependent.
89 		An odd version indicates an in-progress update.
104 		tsc-related quantity to nanoseconds
107 		shift to be used when converting tsc-related
111 		a right shift.
114 		right shift by 32 bits. With this information, guests can
115 		derive per-CPU time by doing::
117 			time = (current_tsc - tsc_timestamp)
121 				time >>= -tsc_shift;
132 		+-----------+--------------+----------------------------------+
134 		+-----------+--------------+----------------------------------+
138 		+-----------+--------------+----------------------------------+
142 		+-----------+--------------+----------------------------------+
195 	Bits 63-6 hold 64-byte aligned physical address of a 64 byte memory area
210 	Bits 5-4 of the MSR are reserved and should be zero. Bit 0 is set to 1
235 	Bytes 5-7 of 64 byte memory location ('token') will be written to by the
241 	writing to the MSR forces KVM to re-scan its queue and deliver the next
264 	64-byte alignment physical address of a memory area which must be
279 	updates of this structure is arbitrary and implementation-dependent.
290 		in-progress update.
303 		not. Non-zero values mean the vCPU has been preempted. Zero
313 	interrupt is enabled (bit 0 set), bits 63-2 hold a 4-byte aligned
321 	EOI by clearing the bit in guest memory - this location will
346 	Control host-side polling.
349 	Bit 0 enables (1) or disables (0) host-side HLT polling logic.
360 	Bits 0-7: APIC vector for delivery of 'page ready' APF events.
361 	Bits 8-63: Reserved
376 	write '1' to bit 0 of the MSR, this causes the host to re-scan its queue