Lines Matching +full:level +full:- +full:triggered
1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
23 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
28 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
35 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
38 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
41 - index encodes the unique redistributor region index
42 - flags: reserved for future use, currently 0
43 - base field encodes bits [51:16] of the guest physical base address
45 - count encodes the number of redistributors in the region. Must be
65 -E2BIG Address outside of addressable IPA range
66 -EINVAL Incorrectly aligned address, bad redistributor region
68 -EEXIST Address already configured
69 -ENOENT Attempt to read the characteristics of a non existing
71 -ENXIO The group or attribute is unknown/unsupported for this device
73 -EFAULT Invalid user pointer for attr->addr.
85 All distributor regs are (rw, 32-bit) and kvm_device_attr.addr points to a
86 __u32 value. 64-bit registers must be accessed by separately accessing the
89 Writes to read-only registers are ignored by the kernel.
128 registers simply sets the non-reserved bits to the value written.
136 edge triggered interrupt, but may differ for level triggered interrupts.
137 For edge triggered interrupts, once an interrupt becomes pending (whether
140 interrupt is activated or when the guest writes to ICPENDR. A level
141 triggered interrupt may be pending either because the level input is held
143 ISPENDR writes are latched; if the device lowers the line level then the
146 the pending status if the line level is still being held high. (These
148 and ISPENDR registers.) For a level triggered interrupt the value accessed
151 ISPENDR is the logical OR of the latch value and the input line level.
155 combination of the current input line level and the latch state, and cannot
156 be deduced from purely the line level and the value of the ISPENDR
166 -ENXIO Getting or setting this register is not yet supported
167 -EBUSY One or more VCPUs are running
192 All system regs accessed through this API are (rw, 64-bit) and
199 Error -ENXIO is returned when accessed in AArch32 mode.
204 -ENXIO Getting or setting this register is not yet supported
205 -EBUSY VCPU is running
206 -EINVAL Invalid mpidr or register value supplied
221 -EINVAL Value set is out of the expected range
222 -EBUSY Value has already be set.
240 -ENXIO VGIC not properly configured as required prior to calling
242 -ENODEV no online VCPU
243 -ENOMEM memory shortage when allocating vgic internal data
244 -EFAULT Invalid guest ram access
245 -EBUSY One or more VCPUS are running
263 Get/Set the input level of the IRQ line for a set of 32 contiguously
269 bitmap where a set bit means the interrupt level is asserted.
274 supported, will be RAZ/WI. LPIs are always edge-triggered and are
289 -EINVAL vINTID is not multiple of 32 or info field is