Lines Matching +full:dma +full:- +full:requests

1 .. SPDX-License-Identifier: GPL-2.0
23           +--------------Core 0-------+
25           |       |       [Root Port]---[Endpoint]
26           |       |       [Root Port]---[Endpoint]
27           |       |       [Root Port]---[Endpoint]
28     Root Complex  |------Core 1-------+
30           |       |       [Root Port]---[ Switch ]---[Endpoint]
31           |       |       [Root Port]---[Endpoint] `-[Endpoint]
32           |       |       [Root Port]---[Endpoint]
33           +---------------------------+
71 ------------------------
76 - qos_tx_cpl: weight of Tx completion TLPs
77 - qos_tx_np: weight of Tx non-posted TLPs
78 - qos_tx_p: weight of Tx posted TLPs
91 -------------------------
95 - rx_alloc_buf_level: watermark of Rx requested
96 - tx_alloc_buf_level: watermark of Tx requested
127     $ perf record -e hisi_ptt0_2/filter=0x80001,type=1,direction=1,
128       format=1/ -- sleep 5
131 code for event 'filter' is 0x80001) with type of posted TLP requests,
135 ---------
161 -------
167 - 8'b00000001: posted requests (P)
168 - 8'b00000010: non-posted requests (NP)
169 - 8'b00000100: completions (CPL)
175 ------------
183 - 4'b0000: inbound TLPs (P, NP, CPL)
184 - 4'b0001: outbound TLPs (P, NP, CPL)
185 - 4'b0010: outbound TLPs (P, NP, CPL) and inbound TLPs (P, NP, CPL B)
186 - 4'b0011: outbound TLPs (P, NP, CPL) and inbound TLPs (CPL A)
191 - 4'b0000: reserved
192 - 4'b0001: outbound TLPs (P, NP, CPL)
193 - 4'b0010: inbound TLPs (P, NP, CPL B)
194 - 4'b0011: inbound TLPs (CPL A)
198 - completion A (CPL A): completion of CHI/DMA/Native non-posted requests, except for CPL B
199 - completion B (CPL B): completion of DMA remote2local and P2P non-posted requests
202 --------------
208 - 4'b0000: 4DW length per TLP header
209 - 4'b0001: 8DW length per TLP header
214 (Header DW0-3 shown below). For example, the TLP header for Memory
215 Reads with 64-bit addresses is shown in PCIe r5.0, Figure 2-17;
216 the header for Configuration Requests is shown in Figure 2.20, etc.
219 possibly a prefix for a PASID TLP prefix (see Figure 6-20, PCIe r5.0).
227          |---------------------------------------|-------------------|
239 timestamp.  DW1-DW3 of the trace buffer entry contain DW1-DW3
246          |-----|---------|---|---|---|---|-------------|-------------|
253 --------------------
256 by the driver. The hardware accepts 4 DMA address with same size,
257 and writes the buffer sequentially like below. If DMA addr 3 is
261     +->[DMA addr 0]->[DMA addr 1]->[DMA addr 2]->[DMA addr 3]-+
262     +---------------------------------------------------------+
264 Driver will allocate each DMA buffer of 4MiB. The finished buffer
269 adjust the size by specifying the `-m` parameter of the perf command.
272 -----------
274 You can decode the traced data with `perf report -D` command (currently