Lines Matching full:trace

23 :Trace Registers: {CONFIGR + others}
25     Bit select trace features. See ‘mode’ section below. Bits
26     in this will cause equivalent programming of trace config and
32     bitfield up to 32 bits setting trace features.
40 :Trace Registers: All
42     Reset all programming to trace nothing / no logic programmed.
50 :Trace Registers: PRGCTLR, All hardware regs.
53       and enables trace.
55     - = 0 : disable trace hardware.
63 :Trace Registers: None.
75 :Trace Registers: None.
77     When FEAT_TRF is implemented, value of TRFCR_ELx.TS used for trace session. Otherwise -1
89 :Trace Registers: None.
102 :Trace Registers: ACVR[idx, idx+1], VIIECTLR
125 :Trace Registers: ACVR[idx]
138 :Trace Registers: ACVR[idx], VISSCTLR
140     Set a trace start address comparator according to addr_idx.
150 :Trace Registers: ACVR[idx], VISSCTLR
152     Set a trace stop address comparator according to addr_idx.
162 :Trace Registers: ACATR[idx,{6:4}]
176 :Trace Registers: ACATR[idx,{3:2}]
191 :Trace Registers: ACATR[idx,{14:8}]
208 :Trace Registers: ACATR[idx,{1:0}]
218 :Trace Registers: ACVR[idx, idx+1], ACATR[idx], VIIECTLR
234 :Trace Registers: From IDR4
241 :Trace Registers: None
248 :Trace Registers: SSCCR[idx]
261 :Trace Registers: SSCSR[idx]
278 :Trace Registers: SSPCICR[idx]
291 :Trace Registers: VICTLR{23:20}
294     exception filter bits. Setting ‘1’ excludes trace from the
304     Excludes EL2 NS trace.
309 :Trace Registers: VIPCSSCTLR
316 :Trace Registers: BBCTLR
326 :Trace Registers: CCCTLR
337 :Trace Registers: SYNCPR
339     Set trace synchronisation period. Power of 2 value, 0 (off)
345 :Trace Registers: none
357 :Trace Registers: CNTCTLR[idx]
370 :Trace Registers: CNTRLDVR[idx]
383 :Trace Registers: From IDR5
391 :Trace Registers: None
403 :Trace Registers: CIDCVR[idx]
412 :Trace Registers: CIDCCTLR0, CIDCCTLR1, CIDCVR<0-7>
430 :Trace Registers: From IDR4
437 :Trace Registers: None
449 :Trace Registers: VMIDCVR[idx]
458 :Trace Registers: VMIDCCTLR0, VMIDCCTLR1, VMIDCVR<0-7>
473 :Trace Registers: From IDR4
480 :Trace Registers: None.
493 :Trace Registers: RSCTLR[idx]
506 :Trace Registers: From IDR4
513 :Trace Registers: EVENTCTRL0R
527 :Trace Registers: EVENTCTRL1R
529     Choose events which insert event packets into trace stream.
540 :Trace Registers: TSCTLR
553 :Trace Registers: None
560 :Trace Registers: SEQSTR
567 :Trace Registers: SEQEVR[idx]
583 :Trace Registers: SEQRSTEVR
595 :Trace Registers: From IDR5
602 :Trace Registers: From IDR4
609 :Trace Registers: From IDR5
616 :Trace Registers: From IDR4
648 This is a bitfield selection parameter that sets the overall trace mode for the
680     Choosing this option will result in a significant increase in the amount of trace generated -
692     Set to enable cycle accurate trace if supported [IDR0].
721     Set to enable trace return stack use if supported [IDR0].
800     Set default trace setup to exclude kernel mode trace (see note a)
807     Set default trace setup to exclude user space trace (see note a)
811 *Note a)* On startup the ETM is programmed to trace the complete address space
822 data trace. As A-profile data trace is architecturally prohibited in ETMv4,