Lines Matching refs:RX
78 - Programmable TX and RX Watchdog and Coalesce Settings
84 - Frame Preemption for TX and RX
88 RX: WRR, SP)
89 - Flexible RX Parser
166 This parameter changes the default RX DMA packet buffer size.
218 the reception on chips older than the 3.50. New chips have an HW RX Watchdog
380 9) Core is able to perform TX Checksum and/or RX Checksum in HW::
400 15) Force to disable the RX Watchdog feature and switch to NAPI mode::
414 20) Limit the maximum TX and RX FIFO size::
419 21) Use the specified number of TX and RX Queues::
424 22) Use the specified TX and RX scheduling algorithm::
429 23) Internal TX and RX Queue parameters::
534 1) Programmable Burst Length (TX and RX)::
538 2) If set, DMA TX / RX will use this value rather than pbl::
601 For the RX Queues configuration, we have:
689 - ``descriptors_status``: To show the DMA TX/RX descriptor rings