Lines Matching refs:CPU
10 For secondary TLB (non CPU TLB) like IOMMU TLB or device TLB (when device use
11 thing like ATS/PASID to get the IOMMU to walk the CPU page table to access a
41 CPU-thread-0 {try to write to addrA}
42 CPU-thread-1 {try to write to addrB}
43 CPU-thread-2 {}
44 CPU-thread-3 {}
48 CPU-thread-0 {COW_step0: {mmu_notifier_invalidate_range_start(addrA)}}
49 CPU-thread-1 {COW_step0: {mmu_notifier_invalidate_range_start(addrB)}}
50 CPU-thread-2 {}
51 CPU-thread-3 {}
55 CPU-thread-0 {COW_step1: {update page table to point to new page for addrA}}
56 CPU-thread-1 {COW_step1: {update page table to point to new page for addrB}}
57 CPU-thread-2 {}
58 CPU-thread-3 {}
62 CPU-thread-0 {preempted}
63 CPU-thread-1 {preempted}
64 CPU-thread-2 {write to addrA which is a write to new page}
65 CPU-thread-3 {}
69 CPU-thread-0 {preempted}
70 CPU-thread-1 {preempted}
71 CPU-thread-2 {}
72 CPU-thread-3 {write to addrB which is a write to new page}
76 CPU-thread-0 {preempted}
77 CPU-thread-1 {COW_step3: {mmu_notifier_invalidate_range_end(addrB)}}
78 CPU-thread-2 {}
79 CPU-thread-3 {}
83 CPU-thread-0 {preempted}
84 CPU-thread-1 {}
85 CPU-thread-2 {}
86 CPU-thread-3 {}