Lines Matching +full:interrupts +full:- +full:extended

1 .. SPDX-License-Identifier: GPL-2.0
7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
9 Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
17 and there are two models of hierarchy (legacy model and extended model).
22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
27      +-----+     +---------+     +-------+
28      | IPI | --> | CPUINTC | <-- | Timer |
29      +-----+     +---------+     +-------+
32                  +---------+     +-------+
33                  | LIOINTC | <-- | UARTs |
34                  +---------+     +-------+
37                 +-----------+
39                 +-----------+
42            +---------+ +---------+
43            | PCH-PIC | | PCH-MSI |
44            +---------+ +---------+
47      +---------+ +---------+ +---------+
48      | PCH-LPC | | Devices | | Devices |
49      +---------+ +---------+ +---------+
52      +---------+
54      +---------+
56 Extended IRQ model
59 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
60 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
64           +-----+     +---------+     +-------+
65           | IPI | --> | CPUINTC | <-- | Timer |
66           +-----+     +---------+     +-------+
69                 +---------+ +---------+     +-------+
70                 | EIOINTC | | LIOINTC | <-- | UARTs |
71                 +---------+ +---------+     +-------+
74           +---------+ +---------+
75           | PCH-PIC | | PCH-MSI |
76           +---------+ +---------+
79     +---------+ +---------+ +---------+
80     | PCH-LPC | | Devices | | Devices |
81     +---------+ +---------+ +---------+
84     +---------+
86     +---------+
88 ACPI-related definitions
115 PCH-PIC::
121 PCH-MSI::
127 PCH-LPC::
136 Documentation of Loongson-3A5000:
138 …https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-userm…
140 …https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-userm…
144 …https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-userm…
146 …https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-userm…
149     - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
151     - LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of
153     - EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of
155     - HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of
157     - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
159     - PCH-LPC is "LPC Interrupts" described in Section 24.3 of