Lines Matching +full:display +full:- +full:hub

2 Display Core Next (DCN)
5 To equip our readers with the basic knowledge of how AMD Display Core Next
10 .. kernel-figure:: dc_pipeline_overview.svg
15 * **Display Controller Hub (DCHUB)**: This is the gateway between the Scalable
19 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
24   multiple planes, using global or per-pixel alpha.
27   the display.
32 * **Display Output (DIO)**: Codify the output to the display connected to our
35 * **Display Writeback (DWB)**: It provides the ability to write the output of
36   the display pipe back to memory as video frames.
38 * **Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB
43   the Display Micro-Controller Unit - version B (DMCUB), which is handled via
47   for all of the display controller clock domains.
52 every ASIC has variations around this base model. Notice that the display
54 the SDP as the element from our Data Fabric that feeds the display pipe.
81 be sent to the display via dc_stream and dc_link.
84 ----------------------
86 Display pipeline can be broken down into two components that are usually
100 a one-to-one mapping of the link encoder to PHY, but we can configure the DCN
103 generic pixel stream to a specific display's pixel stream.
106 ---------
114 representation and convert them to a DCN specific floating-point format (i.e.,
115 different from the IEEE floating-point format). In the process, CNVC also
116 applies a degamma function to transform the data from non-linear to linear
117 space to relax the floating-point calculations following. Data would stay in
118 this floating-point format from DPP to OPP.
123 depth format), bit-depth reduction/dithering would kick in. In OPP, we would
128 ---------------------
142 .. kernel-figure:: pipeline_4k_no_split.svg
145 'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since
146 this log can help us to see part of this pipeline behavior in real-time::
164 .. kernel-figure:: pipeline_4k_split.svg
178 From the above example, we now split the display pipeline into two vertical
182 that the pipe configuration can vary a lot according to the display
187 -----------
203 calculated by the Display Mode Library - DML (drivers/gpu/drm/amd/display/dc/dml)
215 Since DCN hardware is double-buffered the DC driver is able to program the
220 .. kernel-figure:: global_sync_vblank.svg
226 updates, i.e. it allows for multiple re-configurations between VUpdate
230 .. kernel-figure:: config_example.svg