Lines Matching +full:scl +full:- +full:open +full:- +full:drain
26 between 0 and n-1, n being the number of GPIOs managed by the chip.
29 example if a system uses a memory-mapped set of I/O-registers where 32 GPIO
30 lines are handled by one bit per line in a 32-bit register, it makes sense to
44 So for example one platform could use global numbers 32-159 for GPIOs, with a
46 global numbers 0..63 with one set of GPIO controllers, 64-79 with another type
47 of GPIO controller, and on one particular board 80-95 with an FPGA. The legacy
49 2000-2063 to identify GPIO lines in a bank of I2C GPIO expanders.
60 - methods to establish GPIO line direction
61 - methods used to access GPIO line values
62 - method to set electrical configuration for a given GPIO line
63 - method to return the IRQ number associated to a given GPIO line
64 - flag saying whether calls to its methods may sleep
65 - optional line names array to identify lines
66 - optional debugfs dump method (showing extra state information)
67 - optional base number (will be automatically assigned if omitted)
68 - optional label for diagnostics and GPIO chip mapping using platform data
76 Often a gpio_chip is part of an instance-specific structure with states not
78 Chips such as audio codecs will have complex non-GPIO states.
92 -----------------------------
97 - Debouncing
98 - Single-ended modes (open drain/open source)
99 - Pull up and pull down resistor enablement
107 ending up in the pin control back-end "behind" the GPIO controller, usually
111 If a pin controller back-end is used, the GPIO controller or hardware
113 numbers on the pin controller so they can properly cross-reference each other.
117 --------------------------------
133 GPIO lines with open drain/source support
134 -----------------------------------------
136 Open drain (CMOS) or open collector (TTL) means the line is not actively driven
137 high: instead you provide the drain/collector as output, so when the transistor
138 is not open, it will present a high-impedance (tristate) to the external rail::
143 ||--- out +--- out
144 in ----|| |/
145 ||--+ in ----|
151 - Level-shifting: to reach a logical level higher than that of the silicon
154 - Inverse wire-OR on an I/O line, for example a GPIO line, making it possible
157 is driving the SCL and SDA lines of an I2C bus, which is by definition a
158 wire-OR bus.
160 Both use cases require that the line be equipped with a pull-up resistor. This
164 The level on the line will go as high as the VDD on the pull-up resistor, which
166 level-shift to the higher VDD.
169 "totem-pole" with one N-MOS and one P-MOS transistor where one of them drives
170 the line high and one of them drives the line low. This is called a push-pull
171 output. The "totem-pole" looks like so::
175 OD ||--+
176 +--/ ---o|| P-MOS-FET
177 | ||--+
178 IN --+ +----- out
179 | ||--+
180 +--/ ----|| N-MOS-FET
181 OS ||--+
187 a push-pull circuit.
190 P-MOS or N-MOS transistor right after the split of the input. As you can see,
191 either transistor will go totally numb if this switch is open. The totem-pole
193 high or low respectively. That is usually how software-controlled open
194 drain/source works.
196 Some GPIO hardware come in open drain / open source configuration. Some are
197 hard-wired lines that will only support open drain or open source no matter
198 what: there is only one transistor there. Some are software-configurable:
199 by flipping a bit in a register the output can be configured as open drain
200 or open source, in practice by flicking open the switches labeled "OD" and "OS"
203 By disabling the P-MOS transistor, the output can be driven between GND and
204 high impedance (open drain), and by disabling the N-MOS transistor, the output
205 can be driven between VDD and high impedance (open source). In the first case,
206 a pull-up resistor is needed on the outgoing rail to complete the circuit, and
207 in the second case, a pull-down resistor is needed on the rail.
209 Hardware that supports open drain or open source or both, can implement a
211 pinconf packed value telling whether to configure the line as open drain,
212 open source or push-pull. This will happen in response to the
217 not support open drain/open source in hardware, the GPIO library will instead
218 use a trick: when a line is set as output, if the line is flagged as open
219 drain, and the IN output value is low, it will be driven low as usual. But
222 achieving an "open drain emulation" of sorts: electrically the behaviour will
226 For open source configuration the same principle is used, just that instead
231 ---------------------------------------------
233 A GPIO line can support pull-up/down using the .set_config() callback. This
234 means that a pull up or pull-down resistor is available on the output of the
237 In discrete designs, a pull-up or pull-down resistor is simply soldered on
240 configured as open drain or open source (see the section above).
244 switch a bit in a register enabling or disabling pull-up or pull-down.
247 pull-up or pull-down resistor, the GPIO chip callback .set_config() will not
251 different pull-up or pull-down resistance values.
262 the header <linux/irq.h>. So this combined driver is utilizing two sub-
280 - CASCADED INTERRUPT CHIPS: this means that the GPIO chip has one common
293 - HIERARCHICAL INTERRUPT CHIPS: this means that each GPIO line has a dedicated
303 - spinlock_t should be replaced with raw_spinlock_t.[1]
304 - If sleepable APIs have to be used, these can be done from the .irq_bus_lock()
310 ----------------------
314 - CHAINED CASCADED GPIO IRQCHIPS: these are usually the type that is embedded on
332 threaded on -RT. As a result, spinlock_t or any sleepable APIs (like PM
337 this way it will become a threaded IRQ handler on -RT and a hard IRQ handler
338 on non-RT (for example, see [3]).
348 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
349 generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, bit));
350 raw_spin_unlock_irqrestore(&bank->wa_lock, wa_lock_flags);
352 - GENERIC CHAINED GPIO IRQCHIPS: these are the same as "CHAINED GPIO irqchips",
362 Realtime considerations: this kind of handlers will be forced threaded on -RT,
364 with IRQ enabled and the same work-around as for "CHAINED GPIO irqchips" can
367 - NESTED THREADED GPIO IRQCHIPS: these are off-chip GPIO expanders and any
391 ----------------------------------------
393 To help out in handling the set-up and management of GPIO irqchips and the
398 under the assumption that your interrupts are 1-to-1-mapped to the
401 .. csv-table::
408 ngpio-1, ngpio-1
423 .. code-block:: c
480 girq = &g->gc.irq;
482 girq->parent_handler = ftgpio_gpio_irq_handler;
483 girq->num_parents = 1;
484 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
486 if (!girq->parents)
487 return -ENOMEM;
488 girq->default_type = IRQ_TYPE_NONE;
489 girq->handler = handle_bad_irq;
490 girq->parents[0] = irq;
492 return devm_gpiochip_add_data(dev, &g->gc, g);
497 .. code-block:: c
554 irq_thread_fn, IRQF_ONESHOT, "my-chip", g);
559 girq = &g->gc.irq;
562 girq->parent_handler = NULL;
563 girq->num_parents = 0;
564 girq->parents = NULL;
565 girq->default_type = IRQ_TYPE_NONE;
566 girq->handler = handle_bad_irq;
568 return devm_gpiochip_add_data(dev, &g->gc, g);
571 In this case the typical set-up will look like this:
573 .. code-block:: c
633 girq = &g->gc.irq;
635 girq->default_type = IRQ_TYPE_NONE;
636 girq->handler = handle_bad_irq;
637 girq->fwnode = g->fwnode;
638 girq->parent_domain = parent;
639 girq->child_to_parent_hwirq = my_gpio_child_to_parent_hwirq;
641 return devm_gpiochip_add_data(dev, &g->gc, g);
654 bit representing line 0..n-1. Drivers can exclude GPIO lines by clearing bits
660 - Make sure to assign all relevant members of the struct gpio_chip so that
664 - Nominally set gpio_irq_chip.handler to handle_bad_irq. Then, if your irqchip
671 -----------------
686 This will prevent the use of non-irq related GPIO APIs until the GPIO IRQ lock
700 ---------------------------
727 Real-Time compliance for GPIO IRQ chips
728 ---------------------------------------
730 Any provider of irqchips needs to be carefully tailored to support Real-Time
732 in mind and do the proper testing to assure they are real time-enabled.
736 The following is a checklist to follow when preparing a driver for real-time
739 - ensure spinlock_t is not used as part irq_chip implementation
740 - ensure that sleepable APIs are not used as part irq_chip implementation
743 - Chained GPIO irqchips: ensure spinlock_t or any sleepable APIs are not used
745 - Generic chained GPIO irqchips: take care about generic_handle_irq() calls and
746 apply corresponding work-around
747 - Chained GPIO irqchips: get rid of the chained IRQ handler and use generic irq
749 - regmap_mmio: it is possible to disable internal locking in regmap by setting
751 - Test your driver with the appropriate in-kernel real-time test cases for both
754 * [1] http://www.spinics.net/lists/linux-omap/msg120425.html
755 * [2] https://lore.kernel.org/r/1443209283-20781-2-git-send-email-grygorii.strashko@ti.com
756 * [3] https://lore.kernel.org/r/1443209283-20781-3-git-send-email-grygorii.strashko@ti.com
759 Requesting self-owned GPIO pins