Lines Matching +full:reset +full:- +full:time +full:- +full:sec

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/realtek,otto-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Sander Vanheule <sander@svanheule.net>
16   interrupt, although the phase 2 interrupt will occur with the system reset.
17   - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
18   - Phase 2: Starts after phase 1 has timed out, and only serves to give the
19     system some time to clean up, or notify others that it's going to reset.
20     During this phase, pinging the WDT has no effect, and a reset is
24   - $ref: watchdog.yaml#
29       - realtek,rtl8380-wdt
30       - realtek,rtl8390-wdt
31       - realtek,rtl9300-wdt
32       - realtek,rtl9310-wdt
42       - description: interrupt specifier for pretimeout
43       - description: interrupt specifier for timeout
45   interrupt-names:
47       - const: phase1
48       - const: phase2
50   realtek,reset-mode:
53       Specify how the system is reset after a timeout. Defaults to "cpu" if
56       - description: Reset the entire chip
58       - description: |
59           Reset the CPU and IPsec engine, but leave other peripherals untouched
61       - description: |
62           Reset the execution pointer, but don't actually reset any hardware
66   - compatible
67   - reg
68   - clocks
69   - interrupts
74   interrupts: [ interrupt-names ]
77   - |
79         compatible = "realtek,rtl8380-wdt";
82         realtek,reset-mode = "soc";
85         timeout-sec = <20>;
87         interrupt-parent = <&rtlintc>;
88         interrupt-names = "phase1", "phase2";