Lines Matching +full:phy +full:- +full:ref +full:- +full:clk
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
27 $ref: usb.yaml#
29 $ref: usb-xhci.yaml#
35 - const: snps,dwc3
36 - const: synopsys,dwc3
49 interrupt-names:
53 - const: dwc_usb3
54 - items:
60 SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
61 PHY is suspended. suspend clocks a small part of the USB3 core when
62 SS PHY in P3. But particular cases may differ from that having less
65 clock-names:
68 - enum: [bus_early, ref, suspend]
69 - true
71 dma-coherent: true
76 usb-phy:
79 - description: USB2/HS PHY
80 - description: USB3/SS PHY
86 phy-names:
91 - usb2-phy
92 - usb3-phy
97 snps,usb2-lpm-disable:
106 snps,usb2-gadget-lpm-disable:
111 snps,dis-start-transfer-quirk:
113 When set, disable isoc START TRANSFER command failure SW work-around
114 for DWC_usb31 version 1.70a-ea06 and prior.
123 snps,has-lpm-erratum:
127 snps,lpm-nyet-threshold:
129 $ref: /schemas/types.yaml#/definitions/uint8
151 description: When set core will delay PHY power change from P0 to P1/P2/P3.
165 description: When set core will set Tx de-emphasis value
170 The value driven to the PHY is controlled by the LTSSM during USB3
172 $ref: /schemas/types.yaml#/definitions/uint8
174 - 0 # -6dB de-emphasis
175 - 1 # -3.5dB de-emphasis
176 - 2 # No de-emphasis
179 description: When set core will disable USB3 suspend phy
183 description: When set core will disable USB2 suspend phy
189 to the PHY.
192 snps,dis-u1-entry-quirk:
196 snps,dis-u2-entry-quirk:
202 When set core will disable receiver detection in PHY P3 power state.
205 snps,dis-u2-freeclk-exists-quirk:
208 PHY doesn't provide a free-running PHY clock.
211 snps,dis-del-phy-power-chg-quirk:
213 When set core will change PHY power from P0 to P1/P2/P3 without delay.
216 snps,dis-tx-ipgap-linecheck-quirk:
220 snps,parkmode-disable-ss-quirk:
231 snps,dis-split-quirk:
234 avoid -EPROTO errors with usbhid on some devices (Hikey 970).
237 snps,gfladj-refclk-lpm-sel-quirk:
242 snps,resume-hs-terminations:
249 snps,is-utmi-l1-suspend:
255 snps,hird-threshold:
257 $ref: /schemas/types.yaml#/definitions/uint8
261 High-Speed PHY interface selection between UTMI+ and ULPI when the
263 $ref: /schemas/types.yaml#/definitions/uint8
266 snps,quirk-frame-length-adjustment:
268 Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
271 $ref: /schemas/types.yaml#/definitions/uint32
275 snps,ref-clock-period-ns:
286 snps,rx-thr-num-pkt-prd:
289 snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
291 $ref: /schemas/types.yaml#/definitions/uint8
295 snps,rx-max-burst-prd:
298 snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
300 $ref: /schemas/types.yaml#/definitions/uint8
304 snps,tx-thr-num-pkt-prd:
307 snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
309 $ref: /schemas/types.yaml#/definitions/uint8
313 snps,tx-max-burst-prd:
316 snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
318 $ref: /schemas/types.yaml#/definitions/uint8
322 tx-fifo-resize:
330 tx-fifo-max-num:
335 $ref: /schemas/types.yaml#/definitions/uint8
338 snps,incr-burst-type-adjustment:
345 $ref: /schemas/types.yaml#/definitions/uint32-array
353 $ref: /schemas/graph.yaml#/properties/port
355 This port is used with the 'usb-role-switch' property to connect the
358 wakeup-source:
359 $ref: /schemas/types.yaml#/definitions/flag
366 - compatible
367 - reg
368 - interrupts
371 - |
376 usb-phy = <&usb2_phy>, <&usb3_phy>;
377 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
379 - |
384 clocks = <&clk 1>, <&clk 2>, <&clk 3>;
385 clock-names = "bus_early", "ref", "suspend";
387 phy-names = "usb2-phy", "usb3-phy";