Lines Matching +full:gcc +full:- +full:msm8994
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Andy Gross <agross@kernel.org>
13 # Select only our matches, not all jedec,ufs-2.0
20 - compatible
25 - enum:
26 - qcom,msm8994-ufshc
27 - qcom,msm8996-ufshc
28 - qcom,msm8998-ufshc
29 - qcom,sc8280xp-ufshc
30 - qcom,sdm845-ufshc
31 - qcom,sm6350-ufshc
32 - qcom,sm8150-ufshc
33 - qcom,sm8250-ufshc
34 - qcom,sm8350-ufshc
35 - qcom,sm8450-ufshc
36 - const: qcom,ufshc
37 - const: jedec,ufs-2.0
43 clock-names:
51 interconnect-names:
53 - const: ufs-ddr
54 - const: cpu-ufs
63 phy-names:
65 - const: ufsphy
67 power-domains:
77 '#reset-cells':
80 reset-names:
82 - const: rst
84 reset-gpios:
90 - compatible
91 - reg
94 - $ref: ufs-common.yaml
96 - if:
101 - qcom,msm8998-ufshc
102 - qcom,sc8280xp-ufshc
103 - qcom,sm8250-ufshc
104 - qcom,sm8350-ufshc
105 - qcom,sm8450-ufshc
111 clock-names:
113 - const: core_clk
114 - const: bus_aggr_clk
115 - const: iface_clk
116 - const: core_clk_unipro
117 - const: ref_clk
118 - const: tx_lane0_sync_clk
119 - const: rx_lane0_sync_clk
120 - const: rx_lane1_sync_clk
125 - if:
130 - qcom,sdm845-ufshc
131 - qcom,sm6350-ufshc
132 - qcom,sm8150-ufshc
138 clock-names:
140 - const: core_clk
141 - const: bus_aggr_clk
142 - const: iface_clk
143 - const: core_clk_unipro
144 - const: ref_clk
145 - const: tx_lane0_sync_clk
146 - const: rx_lane0_sync_clk
147 - const: rx_lane1_sync_clk
148 - const: ice_core_clk
153 - if:
158 - qcom,msm8996-ufshc
164 clock-names:
166 - const: core_clk_src
167 - const: core_clk
168 - const: bus_clk
169 - const: bus_aggr_clk
170 - const: iface_clk
171 - const: core_clk_unipro_src
172 - const: core_clk_unipro
173 - const: core_clk_ice
174 - const: ref_clk
175 - const: tx_lane0_sync_clk
176 - const: rx_lane0_sync_clk
181 # TODO: define clock bindings for qcom,msm8994-ufshc
186 - |
187 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
188 #include <dt-bindings/clock/qcom,rpmh.h>
189 #include <dt-bindings/gpio/gpio.h>
190 #include <dt-bindings/interconnect/qcom,sm8450.h>
191 #include <dt-bindings/interrupt-controller/arm-gic.h>
194 #address-cells = <2>;
195 #size-cells = <2>;
198 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
199 "jedec,ufs-2.0";
203 phy-names = "ufsphy";
204 lanes-per-direction = <2>;
205 #reset-cells = <1>;
206 resets = <&gcc GCC_UFS_PHY_BCR>;
207 reset-names = "rst";
208 reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
210 vcc-supply = <&vreg_l7b_2p5>;
211 vcc-max-microamp = <1100000>;
212 vccq-supply = <&vreg_l9b_1p2>;
213 vccq-max-microamp = <1200000>;
215 power-domains = <&gcc UFS_PHY_GDSC>;
219 interconnect-names = "ufs-ddr", "cpu-ufs";
221 clock-names = "core_clk",
229 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
230 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
231 <&gcc GCC_UFS_PHY_AHB_CLK>,
232 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
234 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
235 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
236 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
237 freq-table-hz = <75000000 300000000>,