Lines Matching +full:ecc +full:- +full:engine

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-NAND flash controller for MediaTek ARM SoCs
10   - Chuanhong Guo <gch981213@gmail.com>
13   The Mediatek SPI-NAND flash controller is an extended version of
15   instructions with one continuous write and one read for up-to 0xa0
16   bytes. It also supports typical SPI-NAND page cache operations
17   in single, dual or quad IO mode with pipelined ECC encoding/decoding
18   using the accompanying ECC engine. There should be only one spi
22   - $ref: /schemas/spi/spi-controller.yaml#
27       - mediatek,mt7622-snand
28       - mediatek,mt7629-snand
32       - description: core registers
36       - description: NFI interrupt
40       - description: clock used for the controller
41       - description: clock used for the SPI bus
43   clock-names:
45       - const: nfi_clk
46       - const: pad_clk
48   nand-ecc-engine:
49     description: device-tree node of the accompanying ECC engine.
53   - compatible
54   - reg
55   - interrupts
56   - clocks
57   - clock-names
58   - nand-ecc-engine
63   - |
64     #include <dt-bindings/interrupt-controller/irq.h>
65     #include <dt-bindings/interrupt-controller/arm-gic.h>
66     #include <dt-bindings/clock/mt7622-clk.h>
68       #address-cells = <2>;
69       #size-cells = <2>;
71         compatible = "mediatek,mt7622-snand";
75         clock-names = "nfi_clk", "pad_clk";
76         nand-ecc-engine = <&bch>;
77         #address-cells = <1>;
78         #size-cells = <0>;
81           compatible = "spi-nand";
83           spi-tx-bus-width = <4>;
84           spi-rx-bus-width = <4>;
85           nand-ecc-engine = <&snfi>;