Lines Matching +full:big +full:- +full:endian
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
20 - fsl,imx35-spdif
21 - fsl,vf610-spdif
22 - fsl,imx6sx-spdif
23 - fsl,imx8qm-spdif
24 - fsl,imx8qxp-spdif
25 - fsl,imx8mq-spdif
26 - fsl,imx8mm-spdif
27 - fsl,imx8mn-spdif
28 - fsl,imx8ulp-spdif
38 - description: DMA controller phandle and request line for RX
39 - description: DMA controller phandle and request line for TX
41 dma-names:
43 - const: rx
44 - const: tx
48 - description: The core clock of spdif controller.
49 - description: Clock for tx0 and rx0.
50 - description: Clock for tx1 and rx1.
51 - description: Clock for tx2 and rx2.
52 - description: Clock for tx3 and rx3.
53 - description: Clock for tx4 and rx4.
54 - description: Clock for tx5 and rx5.
55 - description: Clock for tx6 and rx6.
56 - description: Clock for tx7 and rx7.
57 - description: The spba clock is required when SPDIF is placed as a bus
61 - description: PLL clock source for 8kHz series rate, optional.
62 - description: PLL clock source for 11khz series rate, optional.
65 clock-names:
67 - const: core
68 - const: rxtx0
69 - const: rxtx1
70 - const: rxtx2
71 - const: rxtx3
72 - const: rxtx4
73 - const: rxtx5
74 - const: rxtx6
75 - const: rxtx7
76 - const: spba
77 - const: pll8k
78 - const: pll11k
81 big-endian:
84 If this property is absent, the native endian mode will be in use
85 as default, or the big endian mode will be in use for all the device
86 registers. Set this flag for HCDs with big endian descriptors and big
87 endian registers.
90 - compatible
91 - reg
92 - interrupts
93 - dmas
94 - dma-names
95 - clocks
96 - clock-names
101 - |
103 compatible = "fsl,imx35-spdif";
108 dma-names = "rx", "tx";
114 clock-names = "core", "rxtx0",
119 big-endian;