Lines Matching +full:hardware +full:- +full:triggered
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
16 using a (addr, val) pair and triggered. Messages in the TCS are then sent in
19 The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
25 A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
27 ACTIVE - Triggered by Linux
28 SLEEP - Triggered by F/W
29 WAKE - Triggered by F/W
30 CONTROL - Triggered by F/W
31 See also:: <dt-bindings/soc/qcom,rpmh-rsc.h>
33 The order in which they are described in the DT, should match the hardware
47 const: qcom,rpmh-rsc
61 qcom,drv-id:
66 qcom,tcs-config:
67 $ref: /schemas/types.yaml#/definitions/uint32-matrix
72 - description: |
74 - ACTIVE_TCS
75 - SLEEP_TCS
76 - WAKE_TCS
77 - CONTROL_TCS
79 - description: Number of TCS
82 describe each TCS type. The order of the TCS must match the hardware
85 qcom,tcs-offset:
94 reg-names:
97 - const: drv-0
98 - const: drv-1
99 - const: drv-2
100 - const: drv-3
102 bcm-voter:
103 $ref: /schemas/interconnect/qcom,bcm-voter.yaml#
105 clock-controller:
108 power-controller:
112 '-regulators$':
113 $ref: /schemas/regulator/qcom,rpmh-regulator.yaml#
116 - compatible
117 - interrupts
118 - qcom,drv-id
119 - qcom,tcs-config
120 - qcom,tcs-offset
121 - reg
122 - reg-names
127 - |
134 // TCS-OFFSET: 0xD00
135 #include <dt-bindings/interrupt-controller/arm-gic.h>
136 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
139 compatible = "qcom,rpmh-rsc";
143 reg-names = "drv-0", "drv-1", "drv-2";
148 qcom,tcs-offset = <0xd00>;
149 qcom,drv-id = <2>;
150 qcom,tcs-config = <ACTIVE_TCS 2>,
156 - |
161 // TCS-OFFSET: 0x1C00
162 #include <dt-bindings/interrupt-controller/arm-gic.h>
163 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
166 compatible = "qcom,rpmh-rsc";
168 reg-names = "drv-0";
171 qcom,tcs-offset = <0x1c00>;
172 qcom,drv-id = <0>;
173 qcom,tcs-config = <ACTIVE_TCS 0>,
179 - |
180 #include <dt-bindings/interrupt-controller/arm-gic.h>
181 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
182 #include <dt-bindings/power/qcom-rpmpd.h>
185 compatible = "qcom,rpmh-rsc";
189 reg-names = "drv-0", "drv-1", "drv-2";
194 qcom,tcs-offset = <0xd00>;
195 qcom,drv-id = <2>;
196 qcom,tcs-config = <ACTIVE_TCS 2>,
201 clock-controller {
202 compatible = "qcom,sm8350-rpmh-clk";
203 #clock-cells = <1>;
204 clock-names = "xo";
208 power-controller {
209 compatible = "qcom,sm8350-rpmhpd";
210 #power-domain-cells = <1>;
211 operating-points-v2 = <&rpmhpd_opp_table>;
213 rpmhpd_opp_table: opp-table {
214 compatible = "operating-points-v2";
217 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
221 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
225 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
229 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
233 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
237 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
241 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
245 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
249 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
253 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
258 bcm-voter {
259 compatible = "qcom,bcm-voter";