Lines Matching +full:msm +full:- +full:uartdm +full:- +full:v1
1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm MSM Serial UARTDM
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 The MSM serial UARTDM hardware is designed for high-speed use cases where the
16 transmit and/or receive channels can be offloaded to a dma-engine. From a
17 software perspective it's mostly compatible with the MSM serial UART except
28 - enum:
29 - qcom,msm-uartdm-v1.1
30 - qcom,msm-uartdm-v1.2
31 - qcom,msm-uartdm-v1.3
32 - qcom,msm-uartdm-v1.4
33 - const: qcom,msm-uartdm
38 clock-names:
40 - const: core
41 - const: iface
46 dma-names:
48 - const: tx
49 - const: rx
54 qcom,rx-crci:
58 channel. Required when using DMA for reception with UARTDM v1.3 and
61 qcom,tx-crci:
65 channel. Required when using DMA for transmission with UARTDM v1.3 and
71 - description: Main control registers
72 - description: An optional second register location shall specify the GSBI control region.
75 - compatible
76 - clock-names
77 - clocks
78 - interrupts
79 - reg
84 - $ref: /schemas/serial/serial.yaml#
86 - if:
90 const: qcom,msm-uartdm-v1.3
101 - |
102 #include <dt-bindings/interrupt-controller/arm-gic.h>
105 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
109 clock-names = "core", "iface";
111 dma-names = "tx", "rx";