Lines Matching +full:tegra186 +full:- +full:gpio

3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - if:
16 - required:
17 - aspeed,lpc-io-reg
18 - required:
19 - aspeed,lpc-interrupts
20 - required:
21 - aspeed,sirq-polarity-sense
25 const: aspeed,ast2500-vuart
26 - if:
29 const: mrvl,mmp-uart
32 reg-shift:
35 - reg-shift
36 - if:
41 - enum:
42 - ns8250
43 - ns16450
44 - ns16550
45 - ns16550a
48 - required: [ clock-frequency ]
49 - required: [ clocks ]
54 - const: ns8250
55 - const: ns16450
56 - const: ns16550
57 - const: ns16550a
58 - const: ns16850
59 - const: aspeed,ast2400-vuart
60 - const: aspeed,ast2500-vuart
61 - const: intel,xscale-uart
62 - const: mrvl,pxa-uart
63 - const: nuvoton,wpcm450-uart
64 - const: nuvoton,npcm750-uart
65 - const: nuvoton,npcm845-uart
66 - const: nvidia,tegra20-uart
67 - const: nxp,lpc3220-uart
68 - items:
69 - enum:
70 - exar,xr16l2552
71 - exar,xr16l2551
72 - exar,xr16l2550
73 - const: ns8250
74 - items:
75 - enum:
76 - altr,16550-FIFO32
77 - altr,16550-FIFO64
78 - altr,16550-FIFO128
79 - fsl,16550-FIFO64
80 - fsl,ns16550
81 - andestech,uart16550
82 - nxp,lpc1850-uart
83 - opencores,uart16550-rtlsvn105
84 - ti,da830-uart
85 - const: ns16550a
86 - items:
87 - enum:
88 - ns16750
89 - cavium,octeon-3860-uart
90 - xlnx,xps-uart16550-2.00.b
91 - ralink,rt2880-uart
92 - enum:
93 - ns16550 # Deprecated, unless the FIFO really is broken
94 - ns16550a
95 - items:
96 - enum:
97 - ralink,mt7620a-uart
98 - ralink,rt3052-uart
99 - ralink,rt3883-uart
100 - const: ralink,rt2880-uart
101 - enum:
102 - ns16550 # Deprecated, unless the FIFO really is broken
103 - ns16550a
104 - items:
105 - enum:
106 - mediatek,mt7622-btif
107 - mediatek,mt7623-btif
108 - const: mediatek,mtk-btif
109 - items:
110 - const: mrvl,mmp-uart
111 - const: intel,xscale-uart
112 - items:
113 - enum:
114 - nvidia,tegra30-uart
115 - nvidia,tegra114-uart
116 - nvidia,tegra124-uart
117 - nvidia,tegra210-uart
118 - nvidia,tegra186-uart
119 - nvidia,tegra194-uart
120 - nvidia,tegra234-uart
121 - const: nvidia,tegra20-uart
129 clock-frequency: true
137 current-speed:
141 reg-offset:
146 reg-shift:
149 reg-io-width:
152 device. There are some systems that require 32-bit accesses to the
155 used-by-rtas:
161 no-loopback-test:
166 fifo-size:
170 auto-flow-control:
177 tx-threshold:
182 overrun-throttle-ms:
186 rts-gpios: true
187 cts-gpios: true
188 dtr-gpios: true
189 dsr-gpios: true
190 rng-gpios: true
191 dcd-gpios: true
193 aspeed,sirq-polarity-sense:
194 $ref: /schemas/types.yaml#/definitions/phandle-array
196 Phandle to aspeed,ast2500-scu compatible syscon alongside register
199 applicable to aspeed,ast2500-vuart.
202 aspeed,lpc-io-reg:
205 The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
207 aspeed,lpc-interrupts:
208 $ref: "/schemas/types.yaml#/definitions/uint32-array"
212 A 2-cell property describing the VUART SIRQ number and SIRQ
214 applicable to aspeed,ast2500-vuart.
217 - reg
218 - interrupts
223 - |
228 reg-shift = <2>;
229 clock-frequency = <48000000>;
231 - |
232 #include <dt-bindings/gpio/gpio.h>
237 clock-frequency = <48000000>;
238 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
239 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
240 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
241 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
242 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
243 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
245 - |
246 #include <dt-bindings/clock/aspeed-clock.h>
247 #include <dt-bindings/interrupt-controller/irq.h>
249 compatible = "aspeed,ast2500-vuart";
251 reg-shift = <2>;
254 no-loopback-test;
255 aspeed,lpc-io-reg = <0x3f8>;
256 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;