Lines Matching +full:d +full:- +full:tlb +full:- +full:sets
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
29 - items:
30 - enum:
31 - sifive,rocket0
32 - sifive,bullet0
33 - sifive,e5
34 - sifive,e7
35 - sifive,e71
36 - sifive,u74-mc
37 - sifive,u54
38 - sifive,u74
39 - sifive,u5
40 - sifive,u7
41 - canaan,k210
42 - const: riscv
43 - items:
44 - enum:
45 - sifive,e51
46 - sifive,u54-mc
47 - const: sifive,rocket0
48 - const: riscv
49 - const: riscv # Simulator only
51 Identifies that the hart uses the RISC-V instruction set
54 mmu-type:
57 hart. These values originate from the RISC-V Privileged
62 - riscv,sv32
63 - riscv,sv39
64 - riscv,sv48
65 - riscv,none
67 riscv,cbom-block-size:
74 Identifies the specific RISC-V instruction set architecture
75 supported by the hart. These are documented in the RISC-V
76 User-Level ISA document, available from
83 pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
85 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
86 timebase-frequency: false
88 interrupt-controller:
93 '#interrupt-cells':
97 const: riscv,cpu-intc
99 interrupt-controller: true
102 - '#interrupt-cells'
103 - compatible
104 - interrupt-controller
106 cpu-idle-states:
107 $ref: '/schemas/types.yaml#/definitions/phandle-array'
112 by this hart (see ./idle-states.yaml).
115 - riscv,isa
116 - interrupt-controller
121 - |
124 #address-cells = <1>;
125 #size-cells = <0>;
126 timebase-frequency = <1000000>;
128 clock-frequency = <0>;
131 i-cache-block-size = <64>;
132 i-cache-sets = <128>;
133 i-cache-size = <16384>;
136 cpu_intc0: interrupt-controller {
137 #interrupt-cells = <1>;
138 compatible = "riscv,cpu-intc";
139 interrupt-controller;
143 clock-frequency = <0>;
145 d-cache-block-size = <64>;
146 d-cache-sets = <64>;
147 d-cache-size = <32768>;
148 d-tlb-sets = <1>;
149 d-tlb-size = <32>;
151 i-cache-block-size = <64>;
152 i-cache-sets = <64>;
153 i-cache-size = <32768>;
154 i-tlb-sets = <1>;
155 i-tlb-size = <32>;
156 mmu-type = "riscv,sv39";
159 tlb-split;
160 cpu_intc1: interrupt-controller {
161 #interrupt-cells = <1>;
162 compatible = "riscv,cpu-intc";
163 interrupt-controller;
168 - |
171 #address-cells = <1>;
172 #size-cells = <0>;
178 mmu-type = "riscv,sv48";
179 interrupt-controller {
180 #interrupt-cells = <1>;
181 interrupt-controller;
182 compatible = "riscv,cpu-intc";