Lines Matching +full:0 +full:x03880000
67 Should be either a value of 1 (LockStep mode) or 0 (Split mode) on
69 omitted; and should be either a value of 0 (Split mode) or 2
90 either of them can be configured to appear at that R5F's address 0x0.
163 enum: [0, 1]
167 either a value of 1 (enabled) or 0 (disabled), default is disabled
172 enum: [0, 1]
176 either a value of 1 (enabled) or 0 (disabled), default is enabled if
181 enum: [0, 1]
184 address 0 (from core's view). Should be either a value of 1 (ATCM
185 at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
219 enum: [0, 2]
223 enum: [0, 1]
240 mailbox0: mailbox-0 {
252 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
253 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
254 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
255 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>;
261 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS */
262 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
263 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
264 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */
273 ranges = <0x41000000 0x00 0x41000000 0x20000>,
274 <0x41400000 0x00 0x41400000 0x20000>;
278 reg = <0x41000000 0x00008000>,
279 <0x41010000 0x00008000>;
283 ti,sci-proc-ids = <0x01 0xFF>;
297 reg = <0x41400000 0x00008000>,
298 <0x41410000 0x00008000>;
302 ti,sci-proc-ids = <0x02 0xFF>;