Lines Matching +full:processor +full:- +full:intensive
4 Binding status: Unstable - Subject to changes for DT representation of clocks
7 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
8 is used to offload some of the processor-intensive tasks or algorithms, for
11 The processor cores in the sub-system usually contain additional sub-modules
13 controller, a dedicated local power/sleep controller etc. The DSP processor
18 Each DSP Core sub-system is represented as a single DT node.
21 --------------------
24 - compatible: Should be one of the following,
25 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
27 - reg: Should contain an entry for each value in 'reg-names'.
30 the parent node's '#address-cells' and '#size-cells' values.
32 - reg-names: Should contain strings with the following names, each
37 - interrupts: Should contain the interrupt number used to receive the
39 interrupt-specifier format as dictated by the
40 'interrupt-parent' node.
42 - memory-region: phandle to the reserved memory node to be associated
46 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
50 --------
53 reserved-memory {
54 #address-cells = <1>;
55 #size-cells = <1>;
58 dsp_memory_region: dsp-memory@c3000000 {
59 compatible = "shared-dma-pool";
68 compatible = "ti,da850-dsp";
74 reg-names = "l2sram", "l1pram", "l1dram", "host1cfg",
76 interrupt-parent = <&intc>;
78 memory-region = <&dsp_memory_region>;