Lines Matching +full:big +full:- +full:endian
8 SoC | FTM-PWM endianness
9 --------+-------------------
14 Please see ../regmap/regmap.txt for more detail about how to specify endian
19 - compatible : should be "fsl,<soc>-ftm-pwm" and one of the following
21 - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610
22 - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
23 - reg: Physical base address and length of the controller's registers
24 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
26 - clock-names: Should include the following module clock source entries:
31 - clocks: Must contain a phandle and clock specifier for each entry in
32 clock-names, please see clock/clock-bindings.txt for details of the property
34 - pinctrl-names: Must contain a "default" entry.
35 - pinctrl-NNN: One property must exist for each entry in pinctrl-names.
36 See pinctrl/pinctrl-bindings.txt for details of the property values.
37 - big-endian: Boolean property, required if the FTM PWM registers use a big-
38 endian rather than little-endian layout.
43 compatible = "fsl,vf610-ftm-pwm";
45 #pwm-cells = <3>;
46 clock-names = "ftm_sys", "ftm_ext",
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_pwm0_1>;
54 big-endian;