Lines Matching +full:sm8450 +full:- +full:lpass +full:- +full:lpi +full:- +full:pinctrl
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
8 Low Power Island (LPI) TLMM block
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
15 LPASS LPI IP on most Qualcomm SoCs
19 const: qcom,sm8450-lpass-lpi-pinctrl
23 - description: LPASS LPI TLMM Control and Status registers
24 - description: LPASS LPI pins SLEW registers
28 - description: LPASS Core voting clock
29 - description: LPASS Audio voting clock
31 clock-names:
33 - const: core
34 - const: audio
36 gpio-controller: true
38 '#gpio-cells':
40 include/dt-bindings/gpio/gpio.h
43 gpio-ranges:
48 '-pins$':
51 Pinctrl node's client devices use subnodes for desired pin configuration.
53 $ref: /schemas/pinctrl/pincfg-node.yaml
61 pattern: "^gpio([0-9]|[1-2][0-9]])$"
77 drive-strength:
83 slew-rate:
92 bias-pull-down: true
94 bias-pull-up: true
96 bias-disable: true
98 output-high: true
100 output-low: true
103 - pins
104 - function
109 - $ref: pinctrl.yaml#
112 - compatible
113 - reg
114 - clocks
115 - clock-names
116 - gpio-controller
117 - '#gpio-cells'
118 - gpio-ranges
123 - |
124 #include <dt-bindings/sound/qcom,q6afe.h>
125 pinctrl@3440000 {
126 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
131 clock-names = "core", "audio";
132 gpio-controller;
133 #gpio-cells = <2>;
134 gpio-ranges = <&lpi_tlmm 0 0 23>;