Lines Matching +full:enable +full:- +full:falling +full:- +full:slew +full:- +full:rate
4 pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5 nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
9 - compatible: "nvidia,tegra114-pinmux"
10 - reg: Should contain the register physical address and length for each of
16 - nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
17 - nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
18 - nvidia,lock: Integer. Lock the pin configuration against further changes
20 - nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
21 - nvidia,rcv-sel: Integer. Select VIL/VIH receivers. 0: normal, 1: high.
22 - nvidia,drive-type: Integer. Valid range 0...3.
29 per-pin mux groups:
32 nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
33 nvidia,io-reset and nvidia,rcv-sel.
74 These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
75 nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
76 support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode
77 and nvidia,drive-type.
97 compatible = "nvidia,tegra114-pinmux";
129 pinctrl-names = "default";
130 pinctrl-0 = <&sdmmc4_default>;