Lines Matching +full:j721e +full:- +full:wiz +full:- +full:16 +full:g
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI J721E WIZ (SERDES Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,am64-wiz-10g
19 - ti,j7200-wiz-10g
21 power-domains:
27 description: clock-specifier to represent input to the WIZ
29 clock-names:
32 - const: fck
33 - const: core_ref_clk
34 - const: ext_ref_clk
35 - const: core_ref1_clk
37 num-lanes:
41 "#address-cells":
44 "#size-cells":
47 "#reset-cells":
50 "#clock-cells":
55 assigned-clocks:
59 assigned-clock-parents:
63 assigned-clock-rates:
67 typec-dir-gpios:
70 GPIO to signal Type-C cable orientation for lane swap.
72 achieve the funtionality of an external type-C plug flip mux.
74 typec-dir-debounce-ms:
79 Number of milliseconds to wait before sampling typec-dir-gpio.
81 Type-C spec states minimum CC pin debounce of 100 ms and maximum
84 refclk-dig:
88 WIZ node should have subnode for refclk_dig to select the reference
99 "#clock-cells":
102 assigned-clocks:
105 assigned-clock-parents:
109 - clocks
110 - "#clock-cells"
111 - assigned-clocks
112 - assigned-clock-parents
120 "^pll[0|1]-refclk$":
124 WIZ node should have subnodes for each of the PLLs present in
132 "#clock-cells":
135 assigned-clocks:
138 assigned-clock-parents:
142 - clocks
143 - "#clock-cells"
144 - assigned-clocks
145 - assigned-clock-parents
147 "^cmn-refclk1?-dig-div$":
151 WIZ node should have subnodes for each of the PMA common refclock
160 "#clock-cells":
164 - clocks
165 - "#clock-cells"
167 "^serdes@[0-9a-f]+$":
170 WIZ node should have '1' subnode for the SERDES. It could be either
173 Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
175 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
178 - compatible
179 - power-domains
180 - clocks
181 - clock-names
182 - num-lanes
183 - "#address-cells"
184 - "#size-cells"
185 - "#reset-cells"
186 - ranges
189 - if:
193 const: ti,j7200-wiz-10g
196 - ti,scm
201 - |
202 #include <dt-bindings/soc/ti,sci_pm_domain.h>
204 wiz@5000000 {
205 compatible = "ti,j721e-wiz-16g";
206 #address-cells = <1>;
207 #size-cells = <1>;
208 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
210 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
211 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
212 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
213 num-lanes = <2>;
214 #reset-cells = <1>;
217 pll0-refclk {
219 #clock-cells = <0>;
220 assigned-clocks = <&wiz1_pll0_refclk>;
221 assigned-clock-parents = <&k3_clks 293 13>;
224 pll1-refclk {
226 #clock-cells = <0>;
227 assigned-clocks = <&wiz1_pll1_refclk>;
228 assigned-clock-parents = <&k3_clks 293 0>;
231 cmn-refclk-dig-div {
233 #clock-cells = <0>;
236 cmn-refclk1-dig-div {
238 #clock-cells = <0>;
241 refclk-dig {
244 #clock-cells = <0>;
245 assigned-clocks = <&wiz0_refclk_dig>;
246 assigned-clock-parents = <&k3_clks 292 11>;
250 compatible = "ti,sierra-phy-t0";
251 reg-names = "serdes";
253 #address-cells = <1>;
254 #size-cells = <0>;
256 reset-names = "sierra_reset";
258 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";