Lines Matching +full:0 +full:x5000000
71 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
100 const: 0
120 "^pll[0|1]-refclk$":
133 const: 0
161 const: 0
167 "^serdes@[0-9a-f]+$":
211 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
215 ranges = <0x5000000 0x5000000 0x10000>;
219 #clock-cells = <0>;
225 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
226 #clock-cells = <0>;
228 assigned-clock-parents = <&k3_clks 293 0>;
233 #clock-cells = <0>;
238 #clock-cells = <0>;
242 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
244 #clock-cells = <0>;
252 reg = <0x5000000 0x10000>;
254 #size-cells = <0>;
255 resets = <&serdes_wiz0 0>;