Lines Matching +full:phy +full:- +full:mode

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: CPSW Port's Interface Mode Selection PHY Tree Bindings
11   - Kishon Vijay Abraham I <kishon@ti.com>
16   The interface mode is selected by configuring the MII mode selection register(s)
20                                                +--------------+
21         +-------------------------------+      |SCM           |
22         |                     CPSW      |      |  +---------+ |
23         |        +--------------------------------+gmii_sel | |
24         |        |                      |      |  +---------+ |
25         |   +----v---+     +--------+   |      +--------------+
26         |   |Port 1..<--+-->GMII/MII<------->
28         |   +--------+  |  +--------+   |
30         |               |  +--------+   |
31         |               |  | RMII   <------->
32         |               +-->        |   |
33         |               |  +--------+   |
35         |               |  +--------+   |
36         |               |  | RGMII  <------->
37         |               +-->        |   |
38         |                  +--------+   |
39         +-------------------------------+
41   CPSW Port's Interface Mode Selection PHY describes MII interface mode between
42   CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
44   CPSW Port's Interface Mode Selection PHY device should defined as child device
46   PHY bindings.
51       - ti,am3352-phy-gmii-sel
52       - ti,dra7xx-phy-gmii-sel
53       - ti,am43xx-phy-gmii-sel
54       - ti,dm814-phy-gmii-sel
55       - ti,am654-phy-gmii-sel
56       - ti,j7200-cpsw5g-phy-gmii-sel
61   '#phy-cells': true
63   ti,qsgmii-main-ports:
64     $ref: /schemas/types.yaml#/definitions/uint32-array
66       Required only for QSGMII mode. Array to select the port for
67       QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
76   - if:
81               - ti,dra7xx-phy-gmii-sel
82               - ti,dm814-phy-gmii-sel
83               - ti,am654-phy-gmii-sel
86         '#phy-cells':
90   - if:
96                 - ti,j7200-cpsw5g-phy-gmii-sel
99         ti,qsgmii-main-ports: false
101   - if:
106               - ti,am3352-phy-gmii-sel
107               - ti,am43xx-phy-gmii-sel
110         '#phy-cells':
113             - CPSW port number (starting from 1)
114             - RMII refclk mode
117   - compatible
118   - reg
119   - '#phy-cells'
124   - |
125     phy_gmii_sel: phy@650 {
126         compatible = "ti,am3352-phy-gmii-sel";
128         #phy-cells = <2>;