Lines Matching +full:mux +full:- +full:controls

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14   - Kishon Vijay Abraham I <kishon@ti.com>
19       - ti,phy-am654-serdes
24   reg-names:
26       - const: serdes
28   power-domains:
37   assigned-clocks:
38     $ref: "/schemas/types.yaml#/definitions/phandle-array"
39   assigned-clock-parents:
40     $ref: "/schemas/types.yaml#/definitions/phandle-array"
42   '#phy-cells':
46       include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes lane function.
48   ti,serdes-clk:
52   '#clock-cells':
55   mux-controls:
59   clock-output-names:
61       - description: Clock output names for SERDES 0
63           - const: serdes0_cmu_refclk
64           - const: serdes0_lo_refclk
65           - const: serdes0_ro_refclk
66       - description: Clock output names for SERDES 1
68           - const: serdes1_cmu_refclk
69           - const: serdes1_lo_refclk
70           - const: serdes1_ro_refclk
73   - compatible
74   - reg
75   - power-domains
76   - clocks
77   - assigned-clocks
78   - assigned-clock-parents
79   - ti,serdes-clk
80   - mux-controls
81   - clock-output-names
86   - |
87     #include <dt-bindings/phy/phy-am654-serdes.h>
90       compatible = "ti,phy-am654-serdes";
92       reg-names = "serdes";
93       #phy-cells = <2>;
94       power-domains = <&k3_pds 153>;
97       clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
98       assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
99       assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
100       ti,serdes-clk = <&serdes0_clk>;
101       mux-controls = <&serdes_mux 0>;
102       #clock-cells = <1>;