Lines Matching +full:rk3399 +full:- +full:mipi +full:- +full:dphy +full:- +full:rx0
1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
24 - description: MIPI D-PHY RX0 cfg clock
25 - description: Video in/out general register file clock
27 clock-names:
29 - const: dphy-ref
30 - const: dphy-cfg
31 - const: grf
33 '#phy-cells':
36 power-domains:
41 - compatible
42 - clocks
43 - clock-names
44 - '#phy-cells'
45 - power-domains
50 - |
53 * MIPI D-PHY RX0 use registers in "general register files", it
57 * compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
62 #include <dt-bindings/clock/rk3399-cru.h>
63 #include <dt-bindings/power/rk3399-power.h>
65 mipi_dphy_rx0: mipi-dphy-rx0 {
66 compatible = "rockchip,rk3399-mipi-dphy-rx0";
70 clock-names = "dphy-ref", "dphy-cfg", "grf";
71 power-domains = <&power RK3399_PD_VIO>;
72 #phy-cells = <0>;