Lines Matching +full:rk3568 +full:- +full:pcie3 +full:- +full:phy

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip PCIe v3 phy
10   - Heiko Stuebner <heiko@sntech.de>
15       - rockchip,rk3568-pcie3-phy
24   clock-names:
26       - const: refclk_m
27       - const: refclk_n
28       - const: pclk
30   data-lanes:
33       (controller-number +1 )
34     $ref: /schemas/types.yaml#/definitions/uint32-array
41   "#phy-cells":
47   reset-names:
48     const: phy
50   rockchip,phy-grf:
52     description: phandle to the syscon managing the phy "general register files"
54   rockchip,pipe-grf:
59   - compatible
60   - reg
61   - rockchip,phy-grf
62   - "#phy-cells"
67   - |
68     #include <dt-bindings/clock/rk3568-cru.h>
69     pcie30phy: phy@fe8c0000 {
70       compatible = "rockchip,rk3568-pcie3-phy";
72       #phy-cells = <0>;
76       clock-names = "refclk_m", "refclk_n", "pclk";
78       reset-names = "phy";
79       rockchip,phy-grf = <&pcie30_phy_grf>;