Lines Matching +full:rockchip +full:- +full:pcie +full:- +full:phy

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC Naneng Combo Phy
10   - Heiko Stuebner <heiko@sntech.de>
15       - rockchip,rk3568-naneng-combphy
22       - description: reference clock
23       - description: apb clock
24       - description: pipe clock
26   clock-names:
28       - const: ref
29       - const: apb
30       - const: pipe
34       - description: exclusive PHY reset line
36   rockchip,enable-ssc:
39       The option SSC can be enabled for U3, SATA and PCIE.
42   rockchip,ext-refclk:
45       Many PCIe connections, especially backplane connections,
49       should be used by both ends of the PCIe link.
50       In PCIe mode one can choose to use an internal or an external reference
52       By default the internal clock is selected. The PCIe PHY provides a 100MHz
55       reference clock needs to be provided to the PCIe PHY.
57   rockchip,pipe-grf:
60       Some additional phy settings are accessed through GRF regs.
62   rockchip,pipe-phy-grf:
67   "#phy-cells":
71   - compatible
72   - reg
73   - clocks
74   - clock-names
75   - resets
76   - rockchip,pipe-grf
77   - rockchip,pipe-phy-grf
78   - "#phy-cells"
83   - |
84     #include <dt-bindings/clock/rk3568-cru.h>
87       compatible = "rockchip,rk3568-pipe-grf", "syscon";
92       compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
96     combphy0: phy@fe820000 {
97       compatible = "rockchip,rk3568-naneng-combphy";
102       clock-names = "ref", "apb", "pipe";
103       assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
104       assigned-clock-rates = <100000000>;
106       rockchip,pipe-grf = <&pipegrf>;
107       rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
108       #phy-cells = <1>;